buzzer.map.qmsg

蜂鸣器实验 向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 16 17:57:44 2006 " "Info: Processing started: Thu Feb 16 17:57:44 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off buzzer -c buzzer " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off buzzer -c buzzer" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "buzzer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file buzzer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 buzzer-arch " "Info: Found design unit 1: buzzer-arch" {  } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 buzzer " "Info: Found entity 1: buzzer" {  } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "buzzer " "Info: Elaborating entity \"buzzer\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "buzzer.vhd(150) " "Info: VHDL Case Statement information at buzzer.vhd(150): OTHERS choice is never selected" {  } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/蜂鸣器/buzzer.vhd" 150 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "92 " "Info: Implemented 92 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "89 " "Info: Implemented 89 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 16 17:57:49 2006 " "Info: Processing ended: Thu Feb 16 17:57:49 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}