buzzer.tan.rpt

蜂鸣器实验 向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调

; N/A                                     ; 97.03 MHz ( period = 10.306 ns )                    ; clk_div2[12] ; out_bit_tmp  ; clk        ; clk      ; None                        ; None                      ; 9.597 ns                ;
; N/A                                     ; 97.72 MHz ( period = 10.233 ns )                    ; clk_div2[3]  ; out_bit_tmp  ; clk        ; clk      ; None                        ; None                      ; 9.524 ns                ;
; N/A                                     ; 104.74 MHz ( period = 9.547 ns )                    ; cnt[15]      ; state[2]     ; clk        ; clk      ; None                        ; None                      ; 8.838 ns                ;
; N/A                                     ; 104.78 MHz ( period = 9.544 ns )                    ; state[1]     ; out_bit_tmp  ; clk        ; clk      ; None                        ; None                      ; 8.835 ns                ;
; N/A                                     ; 104.81 MHz ( period = 9.541 ns )                    ; cnt[15]      ; state[1]     ; clk        ; clk      ; None                        ; None                      ; 8.832 ns                ;
; N/A                                     ; 104.82 MHz ( period = 9.540 ns )                    ; cnt[15]      ; state[0]     ; clk        ; clk      ; None                        ; None                      ; 8.831 ns                ;
; N/A                                     ; 105.46 MHz ( period = 9.482 ns )                    ; cnt[12]      ; state[2]     ; clk        ; clk      ; None                        ; None                      ; 8.773 ns                ;
; N/A                                     ; 105.53 MHz ( period = 9.476 ns )                    ; cnt[12]      ; state[1]     ; clk        ; clk      ; None                        ; None                      ; 8.767 ns                ;
; N/A                                     ; 105.54 MHz ( period = 9.475 ns )                    ; cnt[12]      ; state[0]     ; clk        ; clk      ; None                        ; None                      ; 8.766 ns                ;
; N/A                                     ; 106.99 MHz ( period = 9.347 ns )                    ; state[0]     ; clk_div2[11] ; clk        ; clk      ; None                        ; None                      ; 8.638 ns                ;
; N/A                                     ; 106.99 MHz ( period = 9.347 ns )                    ; state[0]     ; clk_div2[10] ; clk        ; clk      ; None                        ; None                      ; 8.638 ns                ;
; N/A                                     ; 106.99 MHz ( period = 9.347 ns )                    ; state[0]     ; clk_div2[9]  ; clk        ; clk      ; None                        ; None                      ; 8.638 ns                ;
; N/A                                     ; 106.99 MHz ( period = 9.347 ns )                    ; state[0]     ; clk_div2[6]  ; clk        ; clk      ; None                        ; None                      ; 8.638 ns                ;
; N/A                                     ; 106.99 MHz ( period = 9.347 ns )                    ; state[0]     ; clk_div2[7]  ; clk        ; clk      ; None                        ; None                      ; 8.638 ns                ;
; N/A                                     ; 106.99 MHz ( period = 9.347 ns )                    ; state[0]     ; clk_div2[8]  ; clk        ; clk      ; None                        ; None                      ; 8.638 ns                ;
; N/A                                     ; 106.99 MHz ( period = 9.347 ns )                    ; state[0]     ; clk_div2[12] ; clk        ; clk      ; None                        ; None                      ; 8.638 ns                ;
; N/A                                     ; 107.15 MHz ( period = 9.333 ns )                    ; cnt[13]      ; state[2]     ; clk        ; clk      ; None                        ; None                      ; 8.624 ns                ;
; N/A                                     ; 107.22 MHz ( period = 9.327 ns )                    ; cnt[13]      ; state[1]     ; clk        ; clk      ; None                        ; None                      ; 8.618 ns                ;
; N/A                                     ; 107.23 MHz ( period = 9.326 ns )                    ; cnt[13]      ; state[0]     ; clk        ; clk      ; None                        ; None                      ; 8.617 ns                ;
; N/A                                     ; 109.82 MHz ( period = 9.106 ns )                    ; cnt[7]       ; state[2]     ; clk        ; clk      ; None                        ; None                      ; 8.397 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;              ;              ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------+
; tco                                                                    ;
+-------+--------------+------------+-------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To      ; From Clock ;
+-------+--------------+------------+-------------+---------+------------+
; N/A   ; None         ; 13.260 ns  ; out_bit_tmp ; out_bit ; clk        ;
+-------+--------------+------------+-------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Feb 16 17:57:58 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off buzzer -c buzzer
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 82.86 MHz between source register "clk_div2[1]" and destination register "clk_div2[11]" (period= 12.069 ns)
    Info: + Longest register to register delay is 11.360 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N5; Fanout = 10; REG Node = 'clk_div2[1]'
        Info: 2: + IC(2.108 ns) + CELL(0.740 ns) = 2.848 ns; Loc. = LC_X9_Y6_N7; Fanout = 2; COMB Node = 'reduce_or~289'
        Info: 3: + IC(1.938 ns) + CELL(0.200 ns) = 4.986 ns; Loc. = LC_X10_Y7_N9; Fanout = 1; COMB Node = 'reduce_or~8'
        Info: 4: + IC(1.931 ns) + CELL(0.200 ns) = 7.117 ns; Loc. = LC_X8_Y7_N2; Fanout = 1; COMB Node = 'clk_div2[0]~1754'
        Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 7.622 ns; Loc. = LC_X8_Y7_N3; Fanout = 1; COMB Node = 'clk_div2[0]~1758'
        Info: 6: + IC(0.710 ns) + CELL(0.200 ns) = 8.532 ns; Loc. = LC_X8_Y7_N0; Fanout = 13; COMB Node = 'clk_div2[0]~1759'
        Info: 7: + IC(1.068 ns) + CELL(1.760 ns) = 11.360 ns; Loc. = LC_X9_Y7_N5; Fanout = 9; REG Node = 'clk_div2[11]'
        Info: Total cell delay = 3.300 ns ( 29.05 % )
        Info: Total interconnect delay = 8.060 ns ( 70.95 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 6.732 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 43; CLK Node = 'clk'
            Info: 2: + IC(4.682 ns) + CELL(0.918 ns) = 6.732 ns; Loc. = LC_X9_Y7_N5; Fanout = 9; REG Node = 'clk_div2[11]'
            Info: Total cell delay = 2.050 ns ( 30.45 % )
            Info: Total interconnect delay = 4.682 ns ( 69.55 % )
        Info: - Longest clock path from clock "clk" to source register is 6.732 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 43; CLK Node = 'clk'
            Info: 2: + IC(4.682 ns) + CELL(0.918 ns) = 6.732 ns; Loc. = LC_X8_Y7_N5; Fanout = 10; REG Node = 'clk_div2[1]'
            Info: Total cell delay = 2.050 ns ( 30.45 % )
            Info: Total interconnect delay = 4.682 ns ( 69.55 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "out_bit" through register "out_bit_tmp" is 13.260 ns
    Info: + Longest clock path from clock "clk" to source register is 6.732 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 43; CLK Node = 'clk'
        Info: 2: + IC(4.682 ns) + CELL(0.918 ns) = 6.732 ns; Loc. = LC_X10_Y7_N6; Fanout = 4; REG Node = 'out_bit_tmp'
        Info: Total cell delay = 2.050 ns ( 30.45 % )
        Info: Total interconnect delay = 4.682 ns ( 69.55 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 6.152 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y7_N6; Fanout = 4; REG Node = 'out_bit_tmp'
        Info: 2: + IC(3.830 ns) + CELL(2.322 ns) = 6.152 ns; Loc. = PIN_75; Fanout = 0; PIN Node = 'out_bit'
        Info: Total cell delay = 2.322 ns ( 37.74 % )
        Info: Total interconnect delay = 3.830 ns ( 62.26 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Feb 16 17:57:59 2006
    Info: Elapsed time: 00:00:02