dial1.tan.qmsg

拨码开关实验 拨码开关8 位0 1 状态在8 位7 段数码管相应位上显示0 或1。

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cnt_scan\[15\] " "Info: Detected ripple clock \"cnt_scan\[15\]\" as buffer" {  } { { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt_scan\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt_scan\[3\] register cnt_scan\[12\] 201.09 MHz 4.973 ns Internal " "Info: Clock \"clk\" has Internal fmax of 201.09 MHz between source register \"cnt_scan\[3\]\" and destination register \"cnt_scan\[12\]\" (period= 4.973 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.264 ns + Longest register register " "Info: + Longest register to register delay is 4.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_scan\[3\] 1 REG LC_X10_Y4_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y4_N5; Fanout = 3; REG Node = 'cnt_scan\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt_scan[3] } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.978 ns) 1.870 ns cnt_scan\[3\]~74 2 COMB LC_X10_Y4_N5 2 " "Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X10_Y4_N5; Fanout = 2; COMB Node = 'cnt_scan\[3\]~74'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.870 ns" { cnt_scan[3] cnt_scan[3]~74 } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 1.993 ns cnt_scan\[4\]~73 3 COMB LC_X10_Y4_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X10_Y4_N6; Fanout = 2; COMB Node = 'cnt_scan\[4\]~73'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { cnt_scan[3]~74 cnt_scan[4]~73 } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.116 ns cnt_scan\[5\]~72 4 COMB LC_X10_Y4_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X10_Y4_N7; Fanout = 2; COMB Node = 'cnt_scan\[5\]~72'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { cnt_scan[4]~73 cnt_scan[5]~72 } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.239 ns cnt_scan\[6\]~71 5 COMB LC_X10_Y4_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X10_Y4_N8; Fanout = 2; COMB Node = 'cnt_scan\[6\]~71'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { cnt_scan[5]~72 cnt_scan[6]~71 } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 2.638 ns cnt_scan\[7\]~70 6 COMB LC_X10_Y4_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X10_Y4_N9; Fanout = 6; COMB Node = 'cnt_scan\[7\]~70'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.399 ns" { cnt_scan[6]~71 cnt_scan[7]~70 } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.626 ns) 4.264 ns cnt_scan\[12\] 7 REG LC_X11_Y4_N4 2 " "Info: 7: + IC(0.000 ns) + CELL(1.626 ns) = 4.264 ns; Loc. = LC_X11_Y4_N4; Fanout = 2; REG Node = 'cnt_scan\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.626 ns" { cnt_scan[7]~70 cnt_scan[12] } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.372 ns ( 79.08 % ) " "Info: Total cell delay = 3.372 ns ( 79.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.892 ns ( 20.92 % ) " "Info: Total interconnect delay = 0.892 ns ( 20.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.264 ns" { cnt_scan[3] cnt_scan[3]~74 cnt_scan[4]~73 cnt_scan[5]~72 cnt_scan[6]~71 cnt_scan[7]~70 cnt_scan[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.264 ns" { cnt_scan[3] cnt_scan[3]~74 cnt_scan[4]~73 cnt_scan[5]~72 cnt_scan[6]~71 cnt_scan[7]~70 cnt_scan[12] } { 0.000ns 0.892ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 1.626ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.323 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 16 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(0.918 ns) 7.323 ns cnt_scan\[12\] 2 REG LC_X11_Y4_N4 2 " "Info: 2: + IC(5.273 ns) + CELL(0.918 ns) = 7.323 ns; Loc. = LC_X11_Y4_N4; Fanout = 2; REG Node = 'cnt_scan\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.191 ns" { clk cnt_scan[12] } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.99 % ) " "Info: Total cell delay = 2.050 ns ( 27.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.273 ns ( 72.01 % ) " "Info: Total interconnect delay = 5.273 ns ( 72.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk cnt_scan[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout cnt_scan[12] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.323 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 16 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(0.918 ns) 7.323 ns cnt_scan\[3\] 2 REG LC_X10_Y4_N5 3 " "Info: 2: + IC(5.273 ns) + CELL(0.918 ns) = 7.323 ns; Loc. = LC_X10_Y4_N5; Fanout = 3; REG Node = 'cnt_scan\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.191 ns" { clk cnt_scan[3] } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.99 % ) " "Info: Total cell delay = 2.050 ns ( 27.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.273 ns ( 72.01 % ) " "Info: Total interconnect delay = 5.273 ns ( 72.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk cnt_scan[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout cnt_scan[3] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk cnt_scan[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout cnt_scan[12] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk cnt_scan[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout cnt_scan[3] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.264 ns" { cnt_scan[3] cnt_scan[3]~74 cnt_scan[4]~73 cnt_scan[5]~72 cnt_scan[6]~71 cnt_scan[7]~70 cnt_scan[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.264 ns" { cnt_scan[3] cnt_scan[3]~74 cnt_scan[4]~73 cnt_scan[5]~72 cnt_scan[6]~71 cnt_scan[7]~70 cnt_scan[12] } { 0.000ns 0.892ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 1.626ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk cnt_scan[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout cnt_scan[12] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk cnt_scan[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout cnt_scan[3] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[6\] en_xhdl\[1\] 21.512 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[6\]\" through register \"en_xhdl\[1\]\" is 21.512 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.423 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.423 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 16 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns cnt_scan\[15\] 2 REG LC_X11_Y4_N7 3 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X11_Y4_N7; Fanout = 3; REG Node = 'cnt_scan\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.567 ns" { clk cnt_scan[15] } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.806 ns) + CELL(0.918 ns) 12.423 ns en_xhdl\[1\] 3 REG LC_X12_Y8_N4 6 " "Info: 3: + IC(3.806 ns) + CELL(0.918 ns) = 12.423 ns; Loc. = LC_X12_Y8_N4; Fanout = 6; REG Node = 'en_xhdl\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.724 ns" { cnt_scan[15] en_xhdl[1] } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 26.92 % ) " "Info: Total cell delay = 3.344 ns ( 26.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.079 ns ( 73.08 % ) " "Info: Total interconnect delay = 9.079 ns ( 73.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.423 ns" { clk cnt_scan[15] en_xhdl[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.423 ns" { clk clk~combout cnt_scan[15] en_xhdl[1] } { 0.000ns 0.000ns 5.273ns 3.806ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.713 ns + Longest register pin " "Info: + Longest register to pin delay is 8.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en_xhdl\[1\] 1 REG LC_X12_Y8_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N4; Fanout = 6; REG Node = 'en_xhdl\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { en_xhdl[1] } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.954 ns) + CELL(0.914 ns) 1.868 ns data4\[1\]~165 2 COMB LC_X12_Y8_N1 7 " "Info: 2: + IC(0.954 ns) + CELL(0.914 ns) = 1.868 ns; Loc. = LC_X12_Y8_N1; Fanout = 7; COMB Node = 'data4\[1\]~165'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.868 ns" { en_xhdl[1] data4[1]~165 } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.197 ns) + CELL(0.914 ns) 3.979 ns Mux1~17 3 COMB LC_X13_Y8_N2 1 " "Info: 3: + IC(1.197 ns) + CELL(0.914 ns) = 3.979 ns; Loc. = LC_X13_Y8_N2; Fanout = 1; COMB Node = 'Mux1~17'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.111 ns" { data4[1]~165 Mux1~17 } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.412 ns) + CELL(2.322 ns) 8.713 ns dataout\[6\] 4 PIN PIN_108 0 " "Info: 4: + IC(2.412 ns) + CELL(2.322 ns) = 8.713 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'dataout\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.734 ns" { Mux1~17 dataout[6] } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.150 ns ( 47.63 % ) " "Info: Total cell delay = 4.150 ns ( 47.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.563 ns ( 52.37 % ) " "Info: Total interconnect delay = 4.563 ns ( 52.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.713 ns" { en_xhdl[1] data4[1]~165 Mux1~17 dataout[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.713 ns" { en_xhdl[1] data4[1]~165 Mux1~17 dataout[6] } { 0.000ns 0.954ns 1.197ns 2.412ns } { 0.000ns 0.914ns 0.914ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.423 ns" { clk cnt_scan[15] en_xhdl[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.423 ns" { clk clk~combout cnt_scan[15] en_xhdl[1] } { 0.000ns 0.000ns 5.273ns 3.806ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.713 ns" { en_xhdl[1] data4[1]~165 Mux1~17 dataout[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.713 ns" { en_xhdl[1] data4[1]~165 Mux1~17 dataout[6] } { 0.000ns 0.954ns 1.197ns 2.412ns } { 0.000ns 0.914ns 0.914ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "datain\[5\] dataout\[6\] 12.169 ns Longest " "Info: Longest tpd from source pin \"datain\[5\]\" to destination pin \"dataout\[6\]\" is 12.169 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns datain\[5\] 1 PIN PIN_62 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_62; Fanout = 1; PIN Node = 'datain\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { datain[5] } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.452 ns) + CELL(0.740 ns) 5.324 ns data4\[1\]~165 2 COMB LC_X12_Y8_N1 7 " "Info: 2: + IC(3.452 ns) + CELL(0.740 ns) = 5.324 ns; Loc. = LC_X12_Y8_N1; Fanout = 7; COMB Node = 'data4\[1\]~165'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.192 ns" { datain[5] data4[1]~165 } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.197 ns) + CELL(0.914 ns) 7.435 ns Mux1~17 3 COMB LC_X13_Y8_N2 1 " "Info: 3: + IC(1.197 ns) + CELL(0.914 ns) = 7.435 ns; Loc. = LC_X13_Y8_N2; Fanout = 1; COMB Node = 'Mux1~17'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.111 ns" { data4[1]~165 Mux1~17 } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.412 ns) + CELL(2.322 ns) 12.169 ns dataout\[6\] 4 PIN PIN_108 0 " "Info: 4: + IC(2.412 ns) + CELL(2.322 ns) = 12.169 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'dataout\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.734 ns" { Mux1~17 dataout[6] } "NODE_NAME" } } { "dial1.vhd" "" { Text "K:/Mars-1270-S Altera/Mars-1270-S-Core-V2.0/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.108 ns ( 41.98 % ) " "Info: Total cell delay = 5.108 ns ( 41.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.061 ns ( 58.02 % ) " "Info: Total interconnect delay = 7.061 ns ( 58.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.169 ns" { datain[5] data4[1]~165 Mux1~17 dataout[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.169 ns" { datain[5] datain[5]~combout data4[1]~165 Mux1~17 dataout[6] } { 0.000ns 0.000ns 3.452ns 1.197ns 2.412ns } { 0.000ns 1.132ns 0.740ns 0.914ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 28 17:41:54 2007 " "Info: Processing ended: Sat Apr 28 17:41:54 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}