dial1.tan.rpt

拨码开关实验 拨码开关8 位0 1 状态在8 位7 段数码管相应位上显示0 或1。

; N/A   ; None              ; 11.172 ns       ; datain[0] ; dataout[4] ;
; N/A   ; None              ; 11.164 ns       ; datain[3] ; dataout[3] ;
; N/A   ; None              ; 11.140 ns       ; datain[5] ; dataout[1] ;
; N/A   ; None              ; 11.055 ns       ; datain[5] ; dataout[3] ;
; N/A   ; None              ; 10.973 ns       ; datain[6] ; dataout[2] ;
; N/A   ; None              ; 10.924 ns       ; datain[6] ; dataout[4] ;
; N/A   ; None              ; 10.872 ns       ; datain[2] ; dataout[6] ;
; N/A   ; None              ; 10.841 ns       ; datain[1] ; dataout[4] ;
; N/A   ; None              ; 10.831 ns       ; datain[6] ; dataout[1] ;
; N/A   ; None              ; 10.810 ns       ; datain[2] ; dataout[5] ;
; N/A   ; None              ; 10.799 ns       ; datain[2] ; dataout[7] ;
; N/A   ; None              ; 10.777 ns       ; datain[4] ; dataout[2] ;
; N/A   ; None              ; 10.764 ns       ; datain[0] ; dataout[2] ;
; N/A   ; None              ; 10.751 ns       ; datain[1] ; dataout[2] ;
; N/A   ; None              ; 10.747 ns       ; datain[6] ; dataout[3] ;
; N/A   ; None              ; 10.621 ns       ; datain[4] ; dataout[1] ;
; N/A   ; None              ; 10.613 ns       ; datain[1] ; dataout[1] ;
; N/A   ; None              ; 10.608 ns       ; datain[0] ; dataout[1] ;
; N/A   ; None              ; 10.537 ns       ; datain[4] ; dataout[3] ;
; N/A   ; None              ; 10.528 ns       ; datain[1] ; dataout[3] ;
; N/A   ; None              ; 10.524 ns       ; datain[0] ; dataout[3] ;
; N/A   ; None              ; 10.472 ns       ; datain[2] ; dataout[2] ;
; N/A   ; None              ; 10.423 ns       ; datain[2] ; dataout[4] ;
; N/A   ; None              ; 10.330 ns       ; datain[2] ; dataout[1] ;
; N/A   ; None              ; 10.246 ns       ; datain[2] ; dataout[3] ;
+-------+-------------------+-----------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Apr 28 17:41:54 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DIAL1 -c DIAL1
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "cnt_scan[15]" as buffer
Info: Clock "clk" has Internal fmax of 201.09 MHz between source register "cnt_scan[3]" and destination register "cnt_scan[12]" (period= 4.973 ns)
    Info: + Longest register to register delay is 4.264 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y4_N5; Fanout = 3; REG Node = 'cnt_scan[3]'
        Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X10_Y4_N5; Fanout = 2; COMB Node = 'cnt_scan[3]~74'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X10_Y4_N6; Fanout = 2; COMB Node = 'cnt_scan[4]~73'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X10_Y4_N7; Fanout = 2; COMB Node = 'cnt_scan[5]~72'
        Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X10_Y4_N8; Fanout = 2; COMB Node = 'cnt_scan[6]~71'
        Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X10_Y4_N9; Fanout = 6; COMB Node = 'cnt_scan[7]~70'
        Info: 7: + IC(0.000 ns) + CELL(1.626 ns) = 4.264 ns; Loc. = LC_X11_Y4_N4; Fanout = 2; REG Node = 'cnt_scan[12]'
        Info: Total cell delay = 3.372 ns ( 79.08 % )
        Info: Total interconnect delay = 0.892 ns ( 20.92 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 7.323 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(5.273 ns) + CELL(0.918 ns) = 7.323 ns; Loc. = LC_X11_Y4_N4; Fanout = 2; REG Node = 'cnt_scan[12]'
            Info: Total cell delay = 2.050 ns ( 27.99 % )
            Info: Total interconnect delay = 5.273 ns ( 72.01 % )
        Info: - Longest clock path from clock "clk" to source register is 7.323 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(5.273 ns) + CELL(0.918 ns) = 7.323 ns; Loc. = LC_X10_Y4_N5; Fanout = 3; REG Node = 'cnt_scan[3]'
            Info: Total cell delay = 2.050 ns ( 27.99 % )
            Info: Total interconnect delay = 5.273 ns ( 72.01 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "dataout[6]" through register "en_xhdl[1]" is 21.512 ns
    Info: + Longest clock path from clock "clk" to source register is 12.423 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X11_Y4_N7; Fanout = 3; REG Node = 'cnt_scan[15]'
        Info: 3: + IC(3.806 ns) + CELL(0.918 ns) = 12.423 ns; Loc. = LC_X12_Y8_N4; Fanout = 6; REG Node = 'en_xhdl[1]'
        Info: Total cell delay = 3.344 ns ( 26.92 % )
        Info: Total interconnect delay = 9.079 ns ( 73.08 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 8.713 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N4; Fanout = 6; REG Node = 'en_xhdl[1]'
        Info: 2: + IC(0.954 ns) + CELL(0.914 ns) = 1.868 ns; Loc. = LC_X12_Y8_N1; Fanout = 7; COMB Node = 'data4[1]~165'
        Info: 3: + IC(1.197 ns) + CELL(0.914 ns) = 3.979 ns; Loc. = LC_X13_Y8_N2; Fanout = 1; COMB Node = 'Mux1~17'
        Info: 4: + IC(2.412 ns) + CELL(2.322 ns) = 8.713 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'dataout[6]'
        Info: Total cell delay = 4.150 ns ( 47.63 % )
        Info: Total interconnect delay = 4.563 ns ( 52.37 % )
Info: Longest tpd from source pin "datain[5]" to destination pin "dataout[6]" is 12.169 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_62; Fanout = 1; PIN Node = 'datain[5]'
    Info: 2: + IC(3.452 ns) + CELL(0.740 ns) = 5.324 ns; Loc. = LC_X12_Y8_N1; Fanout = 7; COMB Node = 'data4[1]~165'
    Info: 3: + IC(1.197 ns) + CELL(0.914 ns) = 7.435 ns; Loc. = LC_X13_Y8_N2; Fanout = 1; COMB Node = 'Mux1~17'
    Info: 4: + IC(2.412 ns) + CELL(2.322 ns) = 12.169 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'dataout[6]'
    Info: Total cell delay = 5.108 ns ( 41.98 % )
    Info: Total interconnect delay = 7.061 ns ( 58.02 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Apr 28 17:41:54 2007
    Info: Elapsed time: 00:00:00