i2c.map.qmsg

7． IIC 接口EEPROM 存取实验 按动开发板键盘某个键CPLD 将拨码开关的数据写入EEPROM 的某个地址

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 12:15:33 2006 " "Info: Processing started: Sat Feb 18 12:15:33 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file i2c.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c-translated " "Info: Found design unit 1: i2c-translated" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "i2c " "Info: Elaborating entity \"i2c\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "addr i2c.vhd(145) " "Warning: VHDL Process Statement warning at i2c.vhd(145): signal or variable \"addr\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"addr\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 145 0 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "writeData_reg\[4\] writeData_reg\[7\] " "Info: Duplicate register \"writeData_reg\[4\]\" merged to single register \"writeData_reg\[7\]\"" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 47 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "writeData_reg\[5\] writeData_reg\[7\] " "Info: Duplicate register \"writeData_reg\[5\]\" merged to single register \"writeData_reg\[7\]\"" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 47 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "writeData_reg\[6\] writeData_reg\[7\] " "Info: Duplicate register \"writeData_reg\[6\]\" merged to single register \"writeData_reg\[7\]\"" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 47 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_scan\[0\] clk_div\[0\] " "Info: Duplicate register \"cnt_scan\[0\]\" merged to single register \"clk_div\[0\]\"" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 31 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "writeData_reg\[7\] data_in GND " "Warning: Reduced register \"writeData_reg\[7\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 47 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "clk_div\[1\] cnt_scan\[1\] " "Info: Duplicate register \"clk_div\[1\]\" merged to single register \"cnt_scan\[1\]\"" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 41 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "lowbit GND " "Warning: Pin \"lowbit\" stuck at GND" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 22 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg_data\[0\] VCC " "Warning: Pin \"seg_data\[0\]\" stuck at VCC" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 24 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 70 -1 0 } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 47 -1 0 } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 47 -1 0 } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 32 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "272 " "Info: Implemented 272 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "251 " "Info: Implemented 251 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 12:15:46 2006 " "Info: Processing ended: Sat Feb 18 12:15:46 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0}  } {  } 0}