i2c.tan.qmsg

7． IIC 接口EEPROM 存取实验 按动开发板键盘某个键CPLD 将拨码开关的数据写入EEPROM 的某个地址

{ "Info" "ITDB_TH_RESULT" "readData_reg\[0\] sda clk 2.132 ns register " "Info: th for register \"readData_reg\[0\]\" (data pin = \"sda\", clock pin = \"clk\") is 2.132 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.720 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 69 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 69; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns readData_reg\[0\] 2 REG LC_X15_Y9_N6 2 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X15_Y9_N6; Fanout = 2; REG Node = 'readData_reg\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "5.588 ns" { clk readData_reg[0] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk readData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout readData_reg[0] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.809 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_78 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_78; Fanout = 1; PIN Node = 'sda'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "" { sda } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sda~0 2 COMB IOC_X17_Y3_N2 5 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X17_Y3_N2; Fanout = 5; COMB Node = 'sda~0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "1.132 ns" { sda sda~0 } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.397 ns) + CELL(0.280 ns) 4.809 ns readData_reg\[0\] 3 REG LC_X15_Y9_N6 2 " "Info: 3: + IC(3.397 ns) + CELL(0.280 ns) = 4.809 ns; Loc. = LC_X15_Y9_N6; Fanout = 2; REG Node = 'readData_reg\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "3.677 ns" { sda~0 readData_reg[0] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns 29.36 % " "Info: Total cell delay = 1.412 ns ( 29.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.397 ns 70.64 % " "Info: Total interconnect delay = 3.397 ns ( 70.64 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "4.809 ns" { sda sda~0 readData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.809 ns" { sda sda~0 readData_reg[0] } { 0.000ns 0.000ns 3.397ns } { 0.000ns 1.132ns 0.280ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk readData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout readData_reg[0] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "4.809 ns" { sda sda~0 readData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.809 ns" { sda sda~0 readData_reg[0] } { 0.000ns 0.000ns 3.397ns } { 0.000ns 1.132ns 0.280ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 12:16:08 2006 " "Info: Processing ended: Sat Feb 18 12:16:08 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}