📄 i2c.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register inner_state\[1\] register sda_buf 79.38 MHz 12.598 ns Internal " "Info: Clock \"clk\" has Internal fmax of 79.38 MHz between source register \"inner_state\[1\]\" and destination register \"sda_buf\" (period= 12.598 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.889 ns + Longest register register " "Info: + Longest register to register delay is 11.889 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inner_state\[1\] 1 REG LC_X15_Y5_N7 25 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y5_N7; Fanout = 25; REG Node = 'inner_state\[1\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "" { inner_state[1] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 44 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.295 ns) + CELL(0.740 ns) 3.035 ns Mux~11484 2 COMB LC_X16_Y9_N6 1 " "Info: 2: + IC(2.295 ns) + CELL(0.740 ns) = 3.035 ns; Loc. = LC_X16_Y9_N6; Fanout = 1; COMB Node = 'Mux~11484'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "3.035 ns" { inner_state[1] Mux~11484 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.879 ns) + CELL(0.200 ns) 5.114 ns Mux~11485 3 COMB LC_X14_Y9_N5 1 " "Info: 3: + IC(1.879 ns) + CELL(0.200 ns) = 5.114 ns; Loc. = LC_X14_Y9_N5; Fanout = 1; COMB Node = 'Mux~11485'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "2.079 ns" { Mux~11484 Mux~11485 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.614 ns) + CELL(0.200 ns) 7.928 ns Mux~11486 4 COMB LC_X16_Y5_N0 1 " "Info: 4: + IC(2.614 ns) + CELL(0.200 ns) = 7.928 ns; Loc. = LC_X16_Y5_N0; Fanout = 1; COMB Node = 'Mux~11486'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "2.814 ns" { Mux~11485 Mux~11486 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 8.433 ns Mux~11492 5 COMB LC_X16_Y5_N1 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 8.433 ns; Loc. = LC_X16_Y5_N1; Fanout = 1; COMB Node = 'Mux~11492'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "0.505 ns" { Mux~11486 Mux~11492 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 8.938 ns Mux~11493 6 COMB LC_X16_Y5_N2 1 " "Info: 6: + IC(0.305 ns) + CELL(0.200 ns) = 8.938 ns; Loc. = LC_X16_Y5_N2; Fanout = 1; COMB Node = 'Mux~11493'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "0.505 ns" { Mux~11492 Mux~11493 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.890 ns) + CELL(1.061 ns) 11.889 ns sda_buf 7 REG LC_X14_Y5_N9 22 " "Info: 7: + IC(1.890 ns) + CELL(1.061 ns) = 11.889 ns; Loc. = LC_X14_Y5_N9; Fanout = 22; REG Node = 'sda_buf'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "2.951 ns" { Mux~11493 sda_buf } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.601 ns 21.88 % " "Info: Total cell delay = 2.601 ns ( 21.88 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.288 ns 78.12 % " "Info: Total interconnect delay = 9.288 ns ( 78.12 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "11.889 ns" { inner_state[1] Mux~11484 Mux~11485 Mux~11486 Mux~11492 Mux~11493 sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.889 ns" { inner_state[1] Mux~11484 Mux~11485 Mux~11486 Mux~11492 Mux~11493 sda_buf } { 0.000ns 2.295ns 1.879ns 2.614ns 0.305ns 0.305ns 1.890ns } { 0.000ns 0.740ns 0.200ns 0.200ns 0.200ns 0.200ns 1.061ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.720 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 69 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 69; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns sda_buf 2 REG LC_X14_Y5_N9 22 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X14_Y5_N9; Fanout = 22; REG Node = 'sda_buf'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "5.588 ns" { clk sda_buf } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.720 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 69 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 69; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns inner_state\[1\] 2 REG LC_X15_Y5_N7 25 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X15_Y5_N7; Fanout = 25; REG Node = 'inner_state\[1\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "5.588 ns" { clk inner_state[1] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 44 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk inner_state[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout inner_state[1] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk inner_state[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout inner_state[1] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 44 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 32 -1 0 } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "11.889 ns" { inner_state[1] Mux~11484 Mux~11485 Mux~11486 Mux~11492 Mux~11493 sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.889 ns" { inner_state[1] Mux~11484 Mux~11485 Mux~11486 Mux~11492 Mux~11493 sda_buf } { 0.000ns 2.295ns 1.879ns 2.614ns 0.305ns 0.305ns 1.890ns } { 0.000ns 0.740ns 0.200ns 0.200ns 0.200ns 0.200ns 1.061ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk inner_state[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout inner_state[1] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "sda_buf sda clk 4.272 ns register " "Info: tsu for register \"sda_buf\" (data pin = \"sda\", clock pin = \"clk\") is 4.272 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.659 ns + Longest pin register " "Info: + Longest pin to register delay is 10.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_78 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_78; Fanout = 1; PIN Node = 'sda'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "" { sda } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sda~0 2 COMB IOC_X17_Y3_N2 5 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X17_Y3_N2; Fanout = 5; COMB Node = 'sda~0'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "1.132 ns" { sda sda~0 } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.658 ns) + CELL(0.200 ns) 3.990 ns sda_buf~92 3 COMB LC_X15_Y5_N0 4 " "Info: 3: + IC(2.658 ns) + CELL(0.200 ns) = 3.990 ns; Loc. = LC_X15_Y5_N0; Fanout = 4; COMB Node = 'sda_buf~92'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "2.858 ns" { sda~0 sda_buf~92 } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.229 ns) + CELL(0.511 ns) 5.730 ns Mux~11469 4 COMB LC_X14_Y5_N0 2 " "Info: 4: + IC(1.229 ns) + CELL(0.511 ns) = 5.730 ns; Loc. = LC_X14_Y5_N0; Fanout = 2; COMB Node = 'Mux~11469'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "1.740 ns" { sda_buf~92 Mux~11469 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.511 ns) 7.009 ns Mux~11502 5 COMB LC_X14_Y5_N3 1 " "Info: 5: + IC(0.768 ns) + CELL(0.511 ns) = 7.009 ns; Loc. = LC_X14_Y5_N3; Fanout = 1; COMB Node = 'Mux~11502'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "1.279 ns" { Mux~11469 Mux~11502 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 7.514 ns Mux~11470 6 COMB LC_X14_Y5_N4 1 " "Info: 6: + IC(0.305 ns) + CELL(0.200 ns) = 7.514 ns; Loc. = LC_X14_Y5_N4; Fanout = 1; COMB Node = 'Mux~11470'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "0.505 ns" { Mux~11502 Mux~11470 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.200 ns) 8.248 ns Mux~11471 7 COMB LC_X14_Y5_N5 1 " "Info: 7: + IC(0.534 ns) + CELL(0.200 ns) = 8.248 ns; Loc. = LC_X14_Y5_N5; Fanout = 1; COMB Node = 'Mux~11471'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "0.734 ns" { Mux~11470 Mux~11471 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 8.753 ns Mux~11472 8 COMB LC_X14_Y5_N6 1 " "Info: 8: + IC(0.305 ns) + CELL(0.200 ns) = 8.753 ns; Loc. = LC_X14_Y5_N6; Fanout = 1; COMB Node = 'Mux~11472'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "0.505 ns" { Mux~11471 Mux~11472 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 9.258 ns Mux~11480 9 COMB LC_X14_Y5_N7 1 " "Info: 9: + IC(0.305 ns) + CELL(0.200 ns) = 9.258 ns; Loc. = LC_X14_Y5_N7; Fanout = 1; COMB Node = 'Mux~11480'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "0.505 ns" { Mux~11472 Mux~11480 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 9.763 ns Mux~11483 10 COMB LC_X14_Y5_N8 1 " "Info: 10: + IC(0.305 ns) + CELL(0.200 ns) = 9.763 ns; Loc. = LC_X14_Y5_N8; Fanout = 1; COMB Node = 'Mux~11483'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "0.505 ns" { Mux~11480 Mux~11483 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 10.659 ns sda_buf 11 REG LC_X14_Y5_N9 22 " "Info: 11: + IC(0.305 ns) + CELL(0.591 ns) = 10.659 ns; Loc. = LC_X14_Y5_N9; Fanout = 22; REG Node = 'sda_buf'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "0.896 ns" { Mux~11483 sda_buf } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.945 ns 37.01 % " "Info: Total cell delay = 3.945 ns ( 37.01 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.714 ns 62.99 % " "Info: Total interconnect delay = 6.714 ns ( 62.99 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "10.659 ns" { sda sda~0 sda_buf~92 Mux~11469 Mux~11502 Mux~11470 Mux~11471 Mux~11472 Mux~11480 Mux~11483 sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.659 ns" { sda sda~0 sda_buf~92 Mux~11469 Mux~11502 Mux~11470 Mux~11471 Mux~11472 Mux~11480 Mux~11483 sda_buf } { 0.000ns 0.000ns 2.658ns 1.229ns 0.768ns 0.305ns 0.534ns 0.305ns 0.305ns 0.305ns 0.305ns } { 0.000ns 1.132ns 0.200ns 0.511ns 0.511ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.591ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.720 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 69 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 69; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns sda_buf 2 REG LC_X14_Y5_N9 22 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X14_Y5_N9; Fanout = 22; REG Node = 'sda_buf'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "5.588 ns" { clk sda_buf } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "10.659 ns" { sda sda~0 sda_buf~92 Mux~11469 Mux~11502 Mux~11470 Mux~11471 Mux~11472 Mux~11480 Mux~11483 sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.659 ns" { sda sda~0 sda_buf~92 Mux~11469 Mux~11502 Mux~11470 Mux~11471 Mux~11472 Mux~11480 Mux~11483 sda_buf } { 0.000ns 0.000ns 2.658ns 1.229ns 0.768ns 0.305ns 0.534ns 0.305ns 0.305ns 0.305ns 0.305ns } { 0.000ns 1.132ns 0.200ns 0.511ns 0.511ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.591ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[1\] en_xhdl3\[0\] 16.793 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[1\]\" through register \"en_xhdl3\[0\]\" is 16.793 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.720 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 69 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 69; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns en_xhdl3\[0\] 2 REG LC_X15_Y9_N4 8 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X15_Y9_N4; Fanout = 8; REG Node = 'en_xhdl3\[0\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "5.588 ns" { clk en_xhdl3[0] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 70 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk en_xhdl3[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout en_xhdl3[0] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 70 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.697 ns + Longest register pin " "Info: + Longest register to pin delay is 9.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en_xhdl3\[0\] 1 REG LC_X15_Y9_N4 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y9_N4; Fanout = 8; REG Node = 'en_xhdl3\[0\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "" { en_xhdl3[0] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 70 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.529 ns) + CELL(0.740 ns) 2.269 ns seg_data_buf\[0\]~538 2 COMB LC_X15_Y9_N6 7 " "Info: 2: + IC(1.529 ns) + CELL(0.740 ns) = 2.269 ns; Loc. = LC_X15_Y9_N6; Fanout = 7; COMB Node = 'seg_data_buf\[0\]~538'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "2.269 ns" { en_xhdl3[0] seg_data_buf[0]~538 } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.222 ns) + CELL(0.740 ns) 4.231 ns reduce_or~2133 3 COMB LC_X16_Y9_N3 1 " "Info: 3: + IC(1.222 ns) + CELL(0.740 ns) = 4.231 ns; Loc. = LC_X16_Y9_N3; Fanout = 1; COMB Node = 'reduce_or~2133'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "1.962 ns" { seg_data_buf[0]~538 reduce_or~2133 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.299 ns) + CELL(0.200 ns) 6.730 ns reduce_or~2136 4 COMB LC_X11_Y10_N0 1 " "Info: 4: + IC(2.299 ns) + CELL(0.200 ns) = 6.730 ns; Loc. = LC_X11_Y10_N0; Fanout = 1; COMB Node = 'reduce_or~2136'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "2.499 ns" { reduce_or~2133 reduce_or~2136 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.645 ns) + CELL(2.322 ns) 9.697 ns seg_data\[1\] 5 PIN PIN_119 0 " "Info: 5: + IC(0.645 ns) + CELL(2.322 ns) = 9.697 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'seg_data\[1\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "2.967 ns" { reduce_or~2136 seg_data[1] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/i2c.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.002 ns 41.27 % " "Info: Total cell delay = 4.002 ns ( 41.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.695 ns 58.73 % " "Info: Total interconnect delay = 5.695 ns ( 58.73 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "9.697 ns" { en_xhdl3[0] seg_data_buf[0]~538 reduce_or~2133 reduce_or~2136 seg_data[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.697 ns" { en_xhdl3[0] seg_data_buf[0]~538 reduce_or~2133 reduce_or~2136 seg_data[1] } { 0.000ns 1.529ns 1.222ns 2.299ns 0.645ns } { 0.000ns 0.740ns 0.740ns 0.200ns 2.322ns } } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "6.720 ns" { clk en_xhdl3[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout en_xhdl3[0] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/i2c总线/" "" "9.697 ns" { en_xhdl3[0] seg_data_buf[0]~538 reduce_or~2133 reduce_or~2136 seg_data[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.697 ns" { en_xhdl3[0] seg_data_buf[0]~538 reduce_or~2133 reduce_or~2136 seg_data[1] } { 0.000ns 1.529ns 1.222ns 2.299ns 0.645ns } { 0.000ns 0.740ns 0.740ns 0.200ns 2.322ns } } } } 0}
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