traffic.tan.qmsg

模拟交通灯实验 模拟路口的红黄绿交通灯的变化过程

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[6\] first\[3\] 20.027 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[6\]\" through register \"first\[3\]\" is 20.027 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.984 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 25 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.679 ns) + CELL(1.294 ns) 7.105 ns div_cnt\[24\] 2 REG LC_X14_Y3_N7 11 " "Info: 2: + IC(4.679 ns) + CELL(1.294 ns) = 7.105 ns; Loc. = LC_X14_Y3_N7; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "5.973 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.961 ns) + CELL(0.918 ns) 10.984 ns first\[3\] 3 REG LC_X11_Y7_N4 4 " "Info: 3: + IC(2.961 ns) + CELL(0.918 ns) = 10.984 ns; Loc. = LC_X11_Y7_N4; Fanout = 4; REG Node = 'first\[3\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "3.879 ns" { div_cnt[24] first[3] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 30.44 % " "Info: Total cell delay = 3.344 ns ( 30.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.640 ns 69.56 % " "Info: Total interconnect delay = 7.640 ns ( 69.56 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "10.984 ns" { clk div_cnt[24] first[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.984 ns" { clk clk~combout div_cnt[24] first[3] } { 0.000ns 0.000ns 4.679ns 2.961ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.667 ns + Longest register pin " "Info: + Longest register to pin delay is 8.667 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns first\[3\] 1 REG LC_X11_Y7_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y7_N4; Fanout = 4; REG Node = 'first\[3\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "" { first[3] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.293 ns) + CELL(0.740 ns) 2.033 ns data4\[3\]~163 2 COMB LC_X12_Y7_N6 7 " "Info: 2: + IC(1.293 ns) + CELL(0.740 ns) = 2.033 ns; Loc. = LC_X12_Y7_N6; Fanout = 7; COMB Node = 'data4\[3\]~163'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "2.033 ns" { first[3] data4[3]~163 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.835 ns) + CELL(0.914 ns) 3.782 ns Mux~467 3 COMB LC_X12_Y7_N4 1 " "Info: 3: + IC(0.835 ns) + CELL(0.914 ns) = 3.782 ns; Loc. = LC_X12_Y7_N4; Fanout = 1; COMB Node = 'Mux~467'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "1.749 ns" { data4[3]~163 Mux~467 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.563 ns) + CELL(2.322 ns) 8.667 ns dataout\[6\] 4 PIN PIN_108 0 " "Info: 4: + IC(2.563 ns) + CELL(2.322 ns) = 8.667 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'dataout\[6\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "4.885 ns" { Mux~467 dataout[6] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.976 ns 45.88 % " "Info: Total cell delay = 3.976 ns ( 45.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.691 ns 54.12 % " "Info: Total interconnect delay = 4.691 ns ( 54.12 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "8.667 ns" { first[3] data4[3]~163 Mux~467 dataout[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.667 ns" { first[3] data4[3]~163 Mux~467 dataout[6] } { 0.000ns 1.293ns 0.835ns 2.563ns } { 0.000ns 0.740ns 0.914ns 2.322ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "10.984 ns" { clk div_cnt[24] first[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.984 ns" { clk clk~combout div_cnt[24] first[3] } { 0.000ns 0.000ns 4.679ns 2.961ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "8.667 ns" { first[3] data4[3]~163 Mux~467 dataout[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.667 ns" { first[3] data4[3]~163 Mux~467 dataout[6] } { 0.000ns 1.293ns 0.835ns 2.563ns } { 0.000ns 0.740ns 0.914ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 11:21:44 2006 " "Info: Processing ended: Sat Feb 18 11:21:44 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0}  } {  } 0}