traffic.tan.qmsg

模拟交通灯实验 模拟路口的红黄绿交通灯的变化过程

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div_cnt\[15\] " "Info: Detected ripple clock \"div_cnt\[15\]\" as buffer" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 22 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div_cnt\[15\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div_cnt\[24\] " "Info: Detected ripple clock \"div_cnt\[24\]\" as buffer" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 22 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div_cnt\[24\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register first\[1\] register second\[1\] 125.49 MHz 7.969 ns Internal " "Info: Clock \"clk\" has Internal fmax of 125.49 MHz between source register \"first\[1\]\" and destination register \"second\[1\]\" (period= 7.969 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.260 ns + Longest register register " "Info: + Longest register to register delay is 7.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns first\[1\] 1 REG LC_X11_Y7_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y7_N6; Fanout = 5; REG Node = 'first\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "" { first[1] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.914 ns) 1.837 ns reduce_or~0 2 COMB LC_X11_Y7_N8 6 " "Info: 2: + IC(0.923 ns) + CELL(0.914 ns) = 1.837 ns; Loc. = LC_X11_Y7_N8; Fanout = 6; COMB Node = 'reduce_or~0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "1.837 ns" { first[1] reduce_or~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.999 ns) + CELL(0.511 ns) 4.347 ns second\[3\]~1006 3 COMB LC_X10_Y7_N5 4 " "Info: 3: + IC(1.999 ns) + CELL(0.511 ns) = 4.347 ns; Loc. = LC_X10_Y7_N5; Fanout = 4; COMB Node = 'second\[3\]~1006'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "2.510 ns" { reduce_or~0 second[3]~1006 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.852 ns) + CELL(1.061 ns) 7.260 ns second\[1\] 4 REG LC_X11_Y6_N0 6 " "Info: 4: + IC(1.852 ns) + CELL(1.061 ns) = 7.260 ns; Loc. = LC_X11_Y6_N0; Fanout = 6; REG Node = 'second\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "2.913 ns" { second[3]~1006 second[1] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.486 ns 34.24 % " "Info: Total cell delay = 2.486 ns ( 34.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.774 ns 65.76 % " "Info: Total interconnect delay = 4.774 ns ( 65.76 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "7.260 ns" { first[1] reduce_or~0 second[3]~1006 second[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.260 ns" { first[1] reduce_or~0 second[3]~1006 second[1] } { 0.000ns 0.923ns 1.999ns 1.852ns } { 0.000ns 0.914ns 0.511ns 1.061ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.984 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 10.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 25 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.679 ns) + CELL(1.294 ns) 7.105 ns div_cnt\[24\] 2 REG LC_X14_Y3_N7 11 " "Info: 2: + IC(4.679 ns) + CELL(1.294 ns) = 7.105 ns; Loc. = LC_X14_Y3_N7; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "5.973 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.961 ns) + CELL(0.918 ns) 10.984 ns second\[1\] 3 REG LC_X11_Y6_N0 6 " "Info: 3: + IC(2.961 ns) + CELL(0.918 ns) = 10.984 ns; Loc. = LC_X11_Y6_N0; Fanout = 6; REG Node = 'second\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "3.879 ns" { div_cnt[24] second[1] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 30.44 % " "Info: Total cell delay = 3.344 ns ( 30.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.640 ns 69.56 % " "Info: Total interconnect delay = 7.640 ns ( 69.56 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "10.984 ns" { clk div_cnt[24] second[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.984 ns" { clk clk~combout div_cnt[24] second[1] } { 0.000ns 0.000ns 4.679ns 2.961ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.984 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 25 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.679 ns) + CELL(1.294 ns) 7.105 ns div_cnt\[24\] 2 REG LC_X14_Y3_N7 11 " "Info: 2: + IC(4.679 ns) + CELL(1.294 ns) = 7.105 ns; Loc. = LC_X14_Y3_N7; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "5.973 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.961 ns) + CELL(0.918 ns) 10.984 ns first\[1\] 3 REG LC_X11_Y7_N6 5 " "Info: 3: + IC(2.961 ns) + CELL(0.918 ns) = 10.984 ns; Loc. = LC_X11_Y7_N6; Fanout = 5; REG Node = 'first\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "3.879 ns" { div_cnt[24] first[1] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 30.44 % " "Info: Total cell delay = 3.344 ns ( 30.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.640 ns 69.56 % " "Info: Total interconnect delay = 7.640 ns ( 69.56 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "10.984 ns" { clk div_cnt[24] first[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.984 ns" { clk clk~combout div_cnt[24] first[1] } { 0.000ns 0.000ns 4.679ns 2.961ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "10.984 ns" { clk div_cnt[24] second[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.984 ns" { clk clk~combout div_cnt[24] second[1] } { 0.000ns 0.000ns 4.679ns 2.961ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "10.984 ns" { clk div_cnt[24] first[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.984 ns" { clk clk~combout div_cnt[24] first[1] } { 0.000ns 0.000ns 4.679ns 2.961ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "traffic.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 26 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "7.260 ns" { first[1] reduce_or~0 second[3]~1006 second[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.260 ns" { first[1] reduce_or~0 second[3]~1006 second[1] } { 0.000ns 0.923ns 1.999ns 1.852ns } { 0.000ns 0.914ns 0.511ns 1.061ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "10.984 ns" { clk div_cnt[24] second[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.984 ns" { clk clk~combout div_cnt[24] second[1] } { 0.000ns 0.000ns 4.679ns 2.961ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/综合实验/交通灯/traffic/" "" "10.984 ns" { clk div_cnt[24] first[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.984 ns" { clk clk~combout div_cnt[24] first[1] } { 0.000ns 0.000ns 4.679ns 2.961ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0}