vga.rpt

Language writes with VHDL demonstrates the design on the monitor the source program用VHDL 语言写的在显示器上显示

-- Equation name is '_LC2_F26', type is buried 
!_LC2_F26 = _LC2_F26~NOT;
_LC2_F26~NOT = LCELL( _EQ029);
  _EQ029 = !_LC1_F30
         # !ll0
         #  ll1
         # !_LC5_F26;

-- Node name is ':824' 
-- Equation name is '_LC4_E32', type is buried 
!_LC4_E32 = _LC4_E32~NOT;
_LC4_E32~NOT = LCELL( _EQ030);
  _EQ030 = !cc3
         # !cc4;

-- Node name is ':871' 
-- Equation name is '_LC1_F30', type is buried 
!_LC1_F30 = _LC1_F30~NOT;
_LC1_F30~NOT = LCELL( _EQ031);
  _EQ031 = !_LC1_F36
         # !ll8
         # !ll7;

-- Node name is ':1098' 
-- Equation name is '_LC5_E23', type is buried 
_LC5_E23 = LCELL( _EQ032);
  _EQ032 = !cc2 & !cc3 & !cc4 & !_LC6_E23;

-- Node name is ':1125' 
-- Equation name is '_LC6_E28', type is buried 
!_LC6_E28 = _LC6_E28~NOT;
_LC6_E28~NOT = LCELL( _EQ033);
  _EQ033 =  cc3
         #  cc4
         #  cc1 &  cc2;

-- Node name is ':1152' 
-- Equation name is '_LC5_E28', type is buried 
_LC5_E28 = LCELL( _EQ034);
  _EQ034 = !cc2 & !cc4 &  _LC3_E29
         # !cc3 & !cc4;

-- Node name is ':1182' 
-- Equation name is '_LC2_E32', type is buried 
_LC2_E32 = LCELL( _EQ035);
  _EQ035 = !cc3
         # !cc2;

-- Node name is ':1231' 
-- Equation name is '_LC7_E28', type is buried 
!_LC7_E28 = _LC7_E28~NOT;
_LC7_E28~NOT = LCELL( _EQ036);
  _EQ036 =  cc1 &  cc4
         #  cc2 &  cc4
         #  cc3 &  cc4;

-- Node name is ':1270' 
-- Equation name is '_LC3_E29', type is buried 
_LC3_E29 = LCELL( _EQ037);
  _EQ037 = !cc0 & !cc1;

-- Node name is ':1373' 
-- Equation name is '_LC3_E28', type is buried 
_LC3_E28 = LCELL( _EQ038);
  _EQ038 = !_LC8_E28
         #  _LC5_E23
         #  _LC6_E28;

-- Node name is '~1396~1' 
-- Equation name is '~1396~1', location is LC8_E28, type is buried.
-- synthesized logic cell 
!_LC8_E28 = _LC8_E28~NOT;
_LC8_E28~NOT = LCELL( _EQ039);
  _EQ039 = !cc3 & !cc4
         # !cc2 & !cc4
         #  _LC5_E28;

-- Node name is ':1397' 
-- Equation name is '_LC1_E28', type is buried 
_LC1_E28 = LCELL( _EQ040);
  _EQ040 =  _LC7_E28 &  _LC8_E28
         #  _LC5_E23
         #  _LC6_E28;

-- Node name is '~1421~1' 
-- Equation name is '~1421~1', location is LC4_E28, type is buried.
-- synthesized logic cell 
_LC4_E28 = LCELL( _EQ041);
  _EQ041 = !cc3 &  _LC3_E29 & !_LC7_E28
         # !cc2 & !cc3 & !_LC7_E28;

-- Node name is '~1421~2' 
-- Equation name is '~1421~2', location is LC4_E23, type is buried.
-- synthesized logic cell 
_LC4_E23 = LCELL( _EQ042);
  _EQ042 =  cc4 &  _LC4_E28
         # !_LC2_E32 &  _LC4_E28
         # !cc4 & !_LC2_E32 & !_LC6_E23;

-- Node name is ':1421' 
-- Equation name is '_LC2_E28', type is buried 
_LC2_E28 = LCELL( _EQ043);
  _EQ043 =  _LC5_E23
         #  _LC5_E28 & !_LC6_E28
         #  _LC4_E23 & !_LC6_E28;

-- Node name is '~1435~1' 
-- Equation name is '~1435~1', location is LC2_F30, type is buried.
-- synthesized logic cell 
!_LC2_F30 = _LC2_F30~NOT;
_LC2_F30~NOT = LCELL( _EQ044);
  _EQ044 =  ll8
         #  ll7;

-- Node name is ':1435' 
-- Equation name is '_LC6_F36', type is buried 
_LC6_F36 = LCELL( _EQ045);
  _EQ045 =  _LC2_F30 &  _LC5_F36 & !ll6;

-- Node name is ':1448' 
-- Equation name is '_LC5_F36', type is buried 
_LC5_F36 = LCELL( _EQ046);
  _EQ046 = !ll3
         # !ll2
         # !ll5
         # !ll4;

-- Node name is ':1486' 
-- Equation name is '_LC8_F36', type is buried 
!_LC8_F36 = _LC8_F36~NOT;
_LC8_F36~NOT = LCELL( _EQ047);
  _EQ047 = !_LC2_F30
         #  _LC1_F36 &  ll3 &  ll4;

-- Node name is ':1537' 
-- Equation name is '_LC3_F36', type is buried 
_LC3_F36 = LCELL( _EQ048);
  _EQ048 =  _LC7_F36 & !ll6 & !ll8
         # !ll7 & !ll8;

-- Node name is ':1550' 
-- Equation name is '_LC7_F36', type is buried 
_LC7_F36 = LCELL( _EQ049);
  _EQ049 = !ll2 & !ll3
         # !ll5
         # !ll4;

-- Node name is ':1588' 
-- Equation name is '_LC6_F20', type is buried 
!_LC6_F20 = _LC6_F20~NOT;
_LC6_F20~NOT = LCELL( _EQ050);
  _EQ050 =  _LC1_F36 &  ll4 &  ll7
         #  ll8;

-- Node name is '~1591~1' 
-- Equation name is '~1591~1', location is LC1_F36, type is buried.
-- synthesized logic cell 
!_LC1_F36 = _LC1_F36~NOT;
_LC1_F36~NOT = LCELL( _EQ051);
  _EQ051 = !ll5
         # !ll6;

-- Node name is ':1637' 
-- Equation name is '_LC5_F20', type is buried 
_LC5_F20 = LCELL( _EQ052);
  _EQ052 =  _LC3_F20 & !ll6 & !ll7
         # !ll8;

-- Node name is ':1652' 
-- Equation name is '_LC3_F20', type is buried 
_LC3_F20 = LCELL( _EQ053);
  _EQ053 = !ll3 & !ll4
         # !ll2 & !ll4
         # !ll5;

-- Node name is ':1690' 
-- Equation name is '_LC7_F20', type is buried 
!_LC7_F20 = _LC7_F20~NOT;
_LC7_F20~NOT = LCELL( _EQ054);
  _EQ054 =  _LC1_F36 &  ll4
         #  _LC1_F36 &  ll3
         #  ll7;

-- Node name is ':1744' 
-- Equation name is '_LC6_F27', type is buried 
_LC6_F27 = LCELL( _EQ055);
  _EQ055 = !ll5 & !ll6
         #  _LC5_F26 & !ll6
         # !ll7;

-- Node name is ':1756' 
-- Equation name is '_LC5_F26', type is buried 
!_LC5_F26 = _LC5_F26~NOT;
_LC5_F26~NOT = LCELL( _EQ056);
  _EQ056 =  ll4
         #  ll3
         #  ll2;

-- Node name is '~1874~1' 
-- Equation name is '~1874~1', location is LC2_F36, type is buried.
-- synthesized logic cell 
_LC2_F36 = LCELL( _EQ057);
  _EQ057 =  _LC2_F30 &  _LC5_F36 & !ll6
         #  _LC8_F36;

-- Node name is ':1874' 
-- Equation name is '_LC4_F20', type is buried 
_LC4_F20 = LCELL( _EQ058);
  _EQ058 = !_LC8_F20
         #  _LC2_F36;

-- Node name is '~1897~1' 
-- Equation name is '~1897~1', location is LC8_F20, type is buried.
-- synthesized logic cell 
!_LC8_F20 = _LC8_F20~NOT;
_LC8_F20~NOT = LCELL( _EQ059);
  _EQ059 =  _LC3_F36
         #  _LC6_F20;

-- Node name is ':1898' 
-- Equation name is '_LC1_F20', type is buried 
_LC1_F20 = LCELL( _EQ060);
  _EQ060 =  _LC5_F20 &  _LC8_F20
         #  _LC7_F20 &  _LC8_F20
         #  _LC2_F36;

-- Node name is ':1918' 
-- Equation name is '_LC2_F20', type is buried 
_LC2_F20 = LCELL( _EQ061);
  _EQ061 =  _LC5_F20 & !_LC6_F20
         # !_LC6_F20 &  _LC6_F27 & !_LC7_F20;

-- Node name is ':1922' 
-- Equation name is '_LC4_F36', type is buried 
_LC4_F36 = LCELL( _EQ062);
  _EQ062 =  _LC6_F36
         #  _LC3_F36 & !_LC8_F36
         #  _LC2_F20 & !_LC8_F36;

-- Node name is ':1964' 
-- Equation name is '_LC1_E32', type is buried 
_LC1_E32 = LCELL( _EQ063);
  _EQ063 = !_LC1_F30 & !_LC4_E32 &  _LC8_E32 & !md
         # !_LC1_F30 & !_LC4_E32 & !_LC8_E32 &  md;

-- Node name is ':1974' 
-- Equation name is '_LC4_E34', type is buried 
_LC4_E34 = LCELL( _EQ064);
  _EQ064 = !_LC1_F30 & !_LC4_E32 &  _LC5_E32 & !md
         # !_LC1_F30 & !_LC4_E32 & !_LC5_E32 &  md;

-- Node name is ':1984' 
-- Equation name is '_LC1_E34', type is buried 
_LC1_E34 = LCELL( _EQ065);
  _EQ065 = !_LC1_F30 &  _LC3_E32 & !_LC4_E32 & !md
         # !_LC1_F30 & !_LC3_E32 & !_LC4_E32 &  md;



Project Information                                  d:\eda\ep1k30\vga\vga.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 26,040K