idk7a400_board.h

Sharp LH7A400 BSP平台无关部分的代码,有很高的参考价值,尤其是系统架构设计上,设计成移植度很高的BSP.

/***********************************************************************
 * $Workfile:   idk7a400_board.h  $
 * $Revision:   1.1  $
 * $Author:   WellsK  $
 * $Date:   Mar 18 2004 10:51:40  $
 *
 * Project: LogicPD SDK7A400 IDK board definitions
 *
 * Description:
 *     This file contains board specific information for the IDK
 *     board that plugs into the LH7A400 card engine.
 *
 * Revision History:
 * $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh7a400/bsps/sdk7a400/include/idk7a400_board.h-arc  $
 * 
 *    Rev 1.1   Mar 18 2004 10:51:40   WellsK
 * Many changes and fixes for the first released version of the
 * IDK and definitions.
 * 
 *    Rev 1.0   Dec 16 2003 15:24:14   WellsK
 * Initial revision.
 * 
 *
 ***********************************************************************
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 * COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *     CAMAS, WA
 **********************************************************************/
#ifndef IDK7A400_BOARD_H
#define IDK7A400_BOARD_H

#include "abl_types.h"
#include "sdk7a400_board.h"

/***********************************************************************
 * Board or verions specific defines - these need to be customized
 * based on the product for which this is being compiled.
 **********************************************************************/

/* If the target board is an IDK, then the following IDK define needs
   to be enabled. This must be undefined for the SDK. */
#undef IDK

/***********************************************************************
 * IDK CPLD register addresses - slow CPLD base
 **********************************************************************/

/* Base address of slow CPLD IDK registers and remapping selects */
#define IDK_CPLD_SLOW_BASE      (CPLD_SLOW_BASE + 0x02000000)

/* Realtime clock device base address (TI BQ4802LY) */
#define IDK_RTC_BASE            (IDK_CPLD_SLOW_BASE + 0x00000000)

/* Alphanumeric display base address (Agilent HDSP2534) */
#define IDK_ALPHAN_BASE         (IDK_CPLD_SLOW_BASE + 0x00100000)

/* PCMCIA control base address */
#define IDK_PCMCIACNTL_BASE     (IDK_CPLD_SLOW_BASE + 0x00300000)

/* PCMCIA power control base address */
#define IDK_PCMCIAPWR_BASE      (IDK_CPLD_SLOW_BASE + 0x00600000)

/* UART channel A chip select address (TI TL17C752BPT) */
#define IDK_UARTASEL_BASE       (IDK_CPLD_SLOW_BASE + 0x00700000)

/* UART channel B chip select address (TI TL17C752BPT) */
#define IDK_UARTBSEL_BASE       (IDK_CPLD_SLOW_BASE + 0x00800000)

/* Scanning keyboard 1 select address */
#define IDK_KSCANSEL_BASE       (IDK_CPLD_SLOW_BASE + 0x00900000)

/***********************************************************************
 * PCMCIA control registers and bits (used with IDK_PCMCIACNTL_BASE)
 *  Bit 0 = read/write
 *    0 = enable PCM_RDYA_INVRT signal
 *    1 = disable PCM_RDYA_INVRT signal
 *  Bit 1 = read/write
 *    0 = PCM_DRV_INVRTB is high and the power controller is not in
 *        shutdown
 *    1 = PCM_DRV_INVRTB is high and the power controller is in
 *        shutdown
 *  Bit 2 = read/write
 *    0 = Enable PCMCIA slot A status buffer
 *    1 = Disable PCMCIA slot A status buffer
 *  Bit 3 = read/write
 *    0 = Assert reset on PCMCIA slot A
 *    1 = Deassert reset on PCMCIA slot A
 *  Bit 4 = read/write
 *    0 = Enable PCMCIA slot B status buffer
 *    1 = Disable PCMCIA slot B status buffer
 **********************************************************************/

/* PCMCIA slot A ready invert signal */
#define IDK_PCM_RDYA_INVRT      0x0001

/* PCMCIA slot A drive signal */
#define IDK_PCM_DRV_INVRTB      0x0002

/* PCMCIA slot A status buffer enable signal */
#define IDK_PCM_SLOTA_STSEN     0x0004

/* PCMCIA slot A reset signal */
#define IDK_PCM_SLOTA_RESET     0x0008

/* PCMCIA slot B status buffer enable signal */
#define IDK_PCM_SLOTB_STSEN     0x0010

/***********************************************************************
 * PCMCIA control registers and bits (used with IDK_PCMCIAPWR_BASE), see
 * the TI TPS2212 data sheet on what these signals provide.
 *  Bit 0 = read/write, slot A VCC PCMCIA power, CC0A signal
 *  Bit 1 = read/write, slot A VCC PCMCIA power, CC1A signal
 *  Bit 2 = read/write, slot B VCC PCMCIA power, CC0B signal
 *  Bit 3 = read/write, slot B VCC PCMCIA power, CC1B signal
 *  Bit 4 = read/write, slot A VPP PCMCIA power, PP0A signal
 *  Bit 5 = read/write, slot A VPP PCMCIA power, PP1A signal
 *  Bit 6 = read/write, slot B VPP PCMCIA power, PP0B signal
 *  Bit 7 = read/write, slot B VPP PCMCIA power, PP1B signal
 **********************************************************************/

/* VCC value for 0.0v */
#define IDK_PCM_VCC00V          0x0

/* VCC value for 3.3v */
#define IDK_PCM_VCC33V          0x1

/* VCC value for 5.0v */
#define IDK_PCM_VCC50V          0x2

/* VPP values for 0.0v */
#define IDK_PCM_VPP00V          0x0

/* VPP values for 3.3v */
#define IDK_PCM_VPP33V          0x1

/* VPP values for VPPIv */
#define IDK_PCM_VPPIV           0x2

/* VPP values for floating voltage */
#define IDK_PCM_VPPHIZ          0x3

/* Define for programming PCMCIA slot A VCC */
#define IDK_PCM_VCCA(n)         (n & 0x3)

/* Define for programming PCMCIA slot B VCC */
#define IDK_PCM_VCCB(n)         ((n >> 2) & 0x3)

/* Define for programming PCMCIA slot A VPP */
#define IDK_PCM_VPPA(n)         ((n >> 4) & 0x3)

/* Define for programming PCMCIA slot B VPP */
#define IDK_PCM_VPPB(n)         ((n >> 6) & 0x3)

/***********************************************************************
 * IDK CPLD register addresses - fast CPLD base
 **********************************************************************/

/* Base address of fast CPLD IDK registers and remapping selects */
#define IDK_CPLD_FAST_BASE      (SMC_CS7_BASE + 0x02000000)

/* IDK LAN device (chip select) base address */
#define IDK_LAN_BASE            (IDK_CPLD_FAST_BASE + 0x00000000)

/* IDK USD device (chip select) base address */
#define IDK_USB_BASE            (IDK_CPLD_FAST_BASE + 0x00100000)

/* IDK DIP switch (chip select) base address */
#define IDK_DIP_BASE            (IDK_CPLD_FAST_BASE + 0x00200000)

/* IDK LED register base address */
#define IDK_LEDS_BASE           (IDK_CPLD_FAST_BASE + 0x00300000)

/* IDK power management register base address */
#define IDK_PWRMNGT_BASE        (IDK_CPLD_FAST_BASE + 0x00400000)

/* IDK interrupt register 0 base address */
#define IDK_IREG0_BASE          (IDK_CPLD_FAST_BASE + 0x00500000)

/* IDK interrupt mask register 0 base address */
#define IDK_IMSK0_BASE          (IDK_CPLD_FAST_BASE + 0x00600000)

/* IDK interrupt register 1 base address */
#define IDK_IREG1_BASE          (IDK_CPLD_FAST_BASE + 0x00700000)

/* IDK interrupt mask register 1 base address */
#define IDK_IMSK1_BASE          (IDK_CPLD_FAST_BASE + 0x00800000)

/* IDK processor/CODEC type register base address */
#define IDK_PRCCDC_BASE         (IDK_CPLD_FAST_BASE + 0x00900000)

/* IDK IO controller code revision register base address */
#define IDK_IOCREV_BASE         (IDK_CPLD_FAST_BASE + 0x00A00000)

/* IDK scratch register base address */
#define IDK_SCRATCH_BASE        (IDK_CPLD_FAST_BASE + 0x00B00000)

/* IDK control register base address */
#define IDK_CONTROL_BASE        (IDK_CPLD_FAST_BASE + 0x00C00000)

/***********************************************************************
 * IDK LED register and bits
 *  Bit 0 = read/write
 *    0 = Standby mode LED on
 *    1 = Standby mode LED off
 *  Bit 1 = read/write
 *    0 = Sleep mode LED on
 *    1 = Sleep mode LED off
 *  Bit 2 = read/write
 *    0 = Run mode LED on
 *    1 = Run mode LED off
 *  Bit 3 = read/write
 *    0 = Reset mode LED on
 *    1 = Reset mode LED off
 **********************************************************************/

/* IDK Standby mode LED control bit */
#define IDK_LED_STANDBY         0x0001

/* IDK Sleep mode LED control bit */