ram32x32d.v

麻省理工的一个实验室实现的MIPS IP CORE

/* 
Daniel L. Rosenband
9/30/99
*/

// 32x32 dual ported ram (one port read/write, one port read or write

module RAM32X32D (/*AUTOARG*/
   // Outputs
   RData, WpData, 
   // Inputs
   Clk, WData, WAddr, WEN, RAddr0, RAddr1
   );

   output [31:0] RData;		// data from read port
   output [31:0] WpData;	// data from write port
      
   input 	 Clk;
      
   input [31:0]  WData;		// write data
   input [4:0] 	 WAddr;		// write addr
   input 	 WEN;		// write enable
   
   input [4:0] 	 RAddr0;		// read addr
   input [4:0] 	 RAddr1;		// read addr

   wire 	 wEN_L;		// write enable for lower addresses
   wire 	 wEN_H;		// write enable for higher addresses

   assign 	 wEN_L = WEN && (!WAddr[4]);
   assign 	 wEN_H = WEN && WAddr[4];

   RAM32X1D RAM32X1D_0 (.RData (RData[0]),   .WpData	(WpData[0]), .Clk (Clk),          .WData  (WData[0]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_1 (.RData (RData[1]),   .WpData	(WpData[1]), .Clk (Clk),          .WData  (WData[1]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_2 (.RData (RData[2]),   .WpData	(WpData[2]), .Clk (Clk),          .WData  (WData[2]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_3 (.RData (RData[3]),   .WpData	(WpData[3]), .Clk (Clk),          .WData  (WData[3]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_4 (.RData (RData[4]),   .WpData	(WpData[4]), .Clk (Clk),          .WData  (WData[4]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_5 (.RData (RData[5]),   .WpData	(WpData[5]), .Clk (Clk),          .WData  (WData[5]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_6 (.RData (RData[6]),   .WpData	(WpData[6]), .Clk (Clk),          .WData  (WData[6]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_7 (.RData (RData[7]),   .WpData	(WpData[7]), .Clk (Clk),          .WData  (WData[7]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_8 (.RData (RData[8]),   .WpData	(WpData[8]), .Clk (Clk),          .WData  (WData[8]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_9 (.RData (RData[9]),   .WpData	(WpData[9]), .Clk (Clk),          .WData  (WData[9]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_10 (.RData (RData[10]),   .WpData	(WpData[10]), .Clk (Clk),          .WData  (WData[10]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_11 (.RData (RData[11]),   .WpData	(WpData[11]), .Clk (Clk),          .WData  (WData[11]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_12 (.RData (RData[12]),   .WpData	(WpData[12]), .Clk (Clk),          .WData  (WData[12]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_13 (.RData (RData[13]),   .WpData	(WpData[13]), .Clk (Clk),          .WData  (WData[13]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_14 (.RData (RData[14]),   .WpData	(WpData[14]), .Clk (Clk),          .WData  (WData[14]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr0[4:0]));
   RAM32X1D RAM32X1D_15 (.RData (RData[15]),   .WpData	(WpData[15]), .Clk (Clk),          .WData  (WData[15]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_16 (.RData (RData[16]),   .WpData	(WpData[16]), .Clk (Clk),          .WData  (WData[16]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_17 (.RData (RData[17]),   .WpData	(WpData[17]), .Clk (Clk),          .WData  (WData[17]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_18 (.RData (RData[18]),   .WpData	(WpData[18]), .Clk (Clk),          .WData  (WData[18]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_19 (.RData (RData[19]),   .WpData	(WpData[19]), .Clk (Clk),          .WData  (WData[19]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_20 (.RData (RData[20]),   .WpData	(WpData[20]), .Clk (Clk),          .WData  (WData[20]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_21 (.RData (RData[21]),   .WpData	(WpData[21]), .Clk (Clk),          .WData  (WData[21]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_22 (.RData (RData[22]),   .WpData	(WpData[22]), .Clk (Clk),          .WData  (WData[22]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_23 (.RData (RData[23]),   .WpData	(WpData[23]), .Clk (Clk),          .WData  (WData[23]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_24 (.RData (RData[24]),   .WpData	(WpData[24]), .Clk (Clk),          .WData  (WData[24]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_25 (.RData (RData[25]),   .WpData	(WpData[25]), .Clk (Clk),          .WData  (WData[25]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_26 (.RData (RData[26]),   .WpData	(WpData[26]), .Clk (Clk),          .WData  (WData[26]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_27 (.RData (RData[27]),   .WpData	(WpData[27]), .Clk (Clk),          .WData  (WData[27]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_28 (.RData (RData[28]),   .WpData	(WpData[28]), .Clk (Clk),          .WData  (WData[28]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_29 (.RData (RData[29]),   .WpData	(WpData[29]), .Clk (Clk),          .WData  (WData[29]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_30 (.RData (RData[30]),   .WpData	(WpData[30]), .Clk (Clk),          .WData  (WData[30]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));
   RAM32X1D RAM32X1D_31 (.RData (RData[31]),   .WpData	(WpData[31]), .Clk (Clk),          .WData  (WData[31]),
			.WAddr (WAddr[4:0]), .WEN_L (wEN_L), .WEN_H (wEN_H), .RAddr (RAddr1[4:0]));

endmodule // RAM32X32D