📄 spim.scr

📁 麻省理工的一个实验室实现的MIPS IP CORE

💻 SCR

字号:

trace RESET
trace PHI2
trace MEMREAD
trace MEMWRITE
trace REGWRITE
trace BRANCH
trace ZERO
trace PC
trace MIPS_Inst
trace RR1D_BUS
trace RR2D_BUS
trace ALURESULT
trace WRD_BUS
assign ('0') PHI2
assign ('1') RESET
run 1000 
assign ('1') PHI2
run 1000
assign ('0') PHI2
assign ('0') RESET
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000
assign ('0') PHI2
run 1000
assign ('1') PHI2
run 1000

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