control.vhd

来自「麻省理工的一个实验室实现的MIPS IP CORE」· VHDL 代码 · 共 72 行

--
--
-- control module (simulates SPIM control module)
--
--
library Synopsys, IEEE;
use Synopsys.attributes.all;
use  IEEE.STD_LOGIC_1164.all;

entity control is


   port( signal Op : in std_logic_vector(5 downto 0);

                signal RegDst : out std_logic;
                signal ALUSrc : out std_logic;
                signal MemtoReg : out std_logic;
                signal RegWrite : out std_logic;
                signal MemRead : out std_logic;
                signal MemWrite : out std_logic;
                signal Branch : out std_logic;
                signal ALUop0 : out std_logic;
                signal ALUop1 : out std_logic;
                signal phi1,phi2: in std_logic);
		
		
end control;


--
-- SPIM control architecture
--

architecture behavioral of control is
   
   signal  Rformat, Lw, Sw, Beq : std_logic;


begin           -- behavior of SPIM control
------------------------------------------------------------------------------

   

   

		Rformat <= ((NOT Op(5)) AND (NOT Op(4)) AND (NOT Op(3)) AND
				   (NOT Op(2)) AND (NOT Op(1)) AND (NOT Op(0)));

		Lw      <= (    Op(5)) AND (NOT Op(4)) AND (NOT Op(3)) AND
				   (NOT Op(2)) AND (    Op(1)) AND (    Op(0));

		Sw      <= (    Op(5)) AND (NOT Op(4)) AND (    Op(3)) AND
				   (NOT Op(2)) AND (    Op(1)) AND (    Op(0));

		Beq     <= (NOT Op(5)) AND (NOT Op(4)) AND (NOT Op(3)) AND
				   (    Op(2)) AND (NOT Op(1)) AND (NOT Op(0));
   
                RegDst <=  Rformat;
                ALUSrc <=  Lw or Sw;
                MemtoReg <=  Lw;
                RegWrite <=  Rformat or Lw;
                MemRead <=  Lw;
                MemWrite <=  Sw; 
                Branch <=  Beq;
                ALUOp1 <=  Rformat;
                ALUOp0 <=  Beq; 

   

end behavioral;