top_spim.vhd

麻省理工的一个实验室实现的MIPS IP CORE

--
--
-- TOP_SPIM module
--
-- VHDL synthesis and simulation model of MIPS machine
-- as described in chapter 5 of Patterson and Hennessey
-- NOTE: Data paths limited to 8 bits to speed synthesis and
-- simulation.  Registers limited to 8 bits and $R0..$R7
-- Program and Data memory limited to locations 0..7
library Synopsys, IEEE;
use Synopsys.attributes.all;
use IEEE.STD_LOGIC_1164.all;

entity TOP_SPIM is

port(reset,phi1,phi2: in std_logic; PC: out std_logic_vector(7 downto 0);
     Out_Inst: out std_logic_vector(31 downto 0));

end TOP_SPIM;



architecture BEHAVIORAL of TOP_SPIM is

   component Ifetch

   port(Instruction: out std_logic_vector(31 downto 0);
        PCadd : out  std_logic_vector(7 downto 0);
        Addresult : in std_logic_vector(7 downto 0);
        Branch : in std_logic;
        phi1,phi2,reset : in std_logic;
        Zero : in std_logic;
        PCout : out std_logic_vector(7 downto 0));

   end component;

   component Idecode

   port(rr1d_bus : out std_logic_vector(7 downto 0);
        rr2d_bus : out std_logic_vector(7 downto 0);
        Instruction : in std_logic_vector(31 downto 0);
        wrd_bus : in std_logic_vector(7 downto 0);
        RegWrite : in std_logic;
        RegDst : in std_logic;
        Extend : out std_logic_vector(7 downto 0);
        phi1,phi2,reset: in std_logic);

	end component;



   component control


   port( Op : in std_logic_vector(5 downto 0);
                RegDst : out std_logic;
                ALUSrc : out std_logic;
                MemtoReg : out std_logic;
                RegWrite : out std_logic;
                MemRead : out std_logic;
                MemWrite : out std_logic;
                Branch : out std_logic;
                ALUop0 : out std_logic;
                ALUop1 : out std_logic;
                phi1,phi2: in std_logic);
	
	 end component;

   component  Execute


   port(Readdata1 : in std_logic_vector(7 downto 0);
                Readdata2 : in std_logic_vector(7 downto 0);
                Extend : in std_logic_vector(7 downto 0);
                Func_op : in std_logic_vector(5 downto 0);
                ALUOp0 : in std_logic;
                ALUOp1 : in std_logic; 
                ALUSrc : in std_logic;
                Zero : out std_logic;
                ALUResult : out std_logic_vector(7 downto 0);
                ADDResult : out std_logic_vector(7 downto 0);
                PCadd : in std_logic_vector(7 downto 0);
                phi1,phi2: in std_logic);

	end component;

   component dmemory

   port(rd_bus : out std_logic_vector(7 downto 0);
        ra_bus : in std_logic_vector(7 downto 0);
        wd_bus : in std_logic_vector(7 downto 0);
        wadd_bus : in std_logic_vector(7 downto 0);
        MemRead, Memwrite, MemtoReg : in std_logic;
        phi1,phi2,reset: in std_logic);

   end component;

   signal PCadd :  std_logic_vector(7 downto 0);
   signal rr1d_bus : std_logic_vector(7 downto 0);
   signal rr2d_bus : std_logic_vector(7 downto 0);
   signal Extend : std_logic_vector(7 downto 0);
   signal Addresult : std_logic_vector(7 downto 0);
   signal ALUresult : std_logic_vector(7 downto 0);
   signal Branch : std_logic;
   signal Zero : std_logic;
   signal wrd_bus : std_logic_vector(7 downto 0);
   signal RegWrite : std_logic;
   signal RegDst :  std_logic;
   signal ALUSrc :  std_logic;
   signal MemtoReg :  std_logic;
   signal MemRead :  std_logic;
   signal MemWrite :  std_logic;
   signal ALUop :  std_logic_vector(1 downto 0);
   signal MIPS_Inst: std_logic_vector(31 downto 0);

begin
   Out_Inst <= MIPS_Inst;
   IFE : Ifetch

   port map (Instruction => MIPS_Inst,
        PCadd => PCadd,
	Addresult => Addresult,
	Branch => Branch,
        phi1 => phi1, phi2 => phi2, reset => reset,
	Zero => Zero,
	PCout => PC);

   ID : Idecode

   port map (rr1d_bus => rr1d_bus,
	rr2d_bus => rr2d_bus,
        Instruction => MIPS_Inst,
	wrd_bus => wrd_bus,
	RegWrite => RegWrite,
	RegDst => RegDst,
	Extend => Extend,
        phi1 => phi1, phi2 => phi2, reset => reset);

   CTL:   control

   port map ( Op => MIPS_Inst(31 downto 26),
		RegDst => RegDst,
		ALUSrc => ALUSrc,
		MemtoReg => MemtoReg,
		RegWrite => RegWrite,
		MemRead => MemRead,
		MemWrite => MemWrite,
		Branch => Branch,
		ALUop0 => ALUop(0),
		ALUop1 => ALUop(1),
		phi1 => phi1, phi2 => phi2);

   EXE:  Execute


   port map (Readdata1 => rr1d_bus,
		Readdata2 => rr2d_bus,
		Extend => Extend,
                Func_op => MIPS_Inst(5 downto 0),
		ALUOp0 => ALUop(0),
		ALUOp1 => ALUop(1), 
		ALUSrc => ALUSrc,
		Zero => Zero,
		ALUResult => ALUResult,
		ADDResult => ADDResult,
		PCadd => PCadd,
		phi1 => phi1, phi2 => phi2);

   MEM:  dmemory

   port map (rd_bus => wrd_bus,
	ra_bus => ALUResult,
	wd_bus => rr2d_bus,
        wadd_bus => ALUResult,
	MemRead => MemRead, 
	Memwrite => MemWrite, 
	MemtoReg => MemtoReg,
		phi1 => phi1, phi2 => phi2, reset => reset);
 
end behavioral;

configuration SPIM of TOP_SPIM is
for BEHAVIORAL
 for IFE: Ifetch
    use entity work.IFETCH(BEHAVIORAL);
 end for;
 for ID: Idecode
    use entity work.IDECODE(BEHAVIORAL);
 end for;
 for CTL: control
    use entity work.CONTROL(BEHAVIORAL);
 end for;
 for EXE: execute
    use entity work.EXECUTE(BEHAVIORAL);
 end for;
 for MEM: dmemory
    use entity work.DMEMORY(BEHAVIORAL);
 end for;
end for;
end SPIM;