dmemory.vhd

麻省理工的一个实验室实现的MIPS IP CORE

--
--
-- DMEMORY module (provides the data memory for the SPIM computer)
library Synopsys, IEEE;
use Synopsys.attributes.all;
use IEEE.STD_LOGIC_1164.all;

entity dmemory is

 
   port(rd_bus : out std_logic_vector(7 downto 0);
        ra_bus : in std_logic_vector(7 downto 0);
        wd_bus : in std_logic_vector(7 downto 0);
        wadd_bus : in std_logic_vector(7 downto 0);
        MemRead, Memwrite, MemtoReg : in std_logic;
                phi1,phi2,reset: in std_logic);

end dmemory;

--
-- DMEMORY architecture
--

architecture behavioral of dmemory is
	  
          signal mem0,mem1,mem2,mem3,mem4,mem5,mem6,mem7 : std_logic_vector(7 downto 0);
          signal mux : std_logic_vector(7 downto 0);
          signal mem0write, mem1write, mem2write, mem3write : std_logic;
          signal mem4write, mem5write, mem6write, mem7write : std_logic;


begin
-- Read Data Memory
with ra_bus(2 downto 0) select
mux <= mem0 WHEN "000",
	   mem1 WHEN "001",
	   mem2 WHEN "010",
	   mem3 WHEN "011",
	   mem4 WHEN "100",
	   mem5 WHEN "101",
	   mem6 WHEN "110",
           mem7 WHEN "111",
           To_stdlogicvector(X"FF") WHEN others;

-- Mux to skip data memory for Rformat instructions
rd_bus <= ra_bus(7 downto 0) WHEN (MemtoReg='0') ELSE mux WHEN (MemRead='1')
                ELSE To_Stdlogicvector(B"11111111");

-- Write to data memory?
-- The following code sets an initial value and replaces the next line
--dff_v(wd_bus,phi2 AND Memwrite AND (wadd_bus(2 downto 0)="000"),mem0);
mem0write <= '1' When ((Memwrite='1') AND(wadd_bus(2 downto 0)="000"))
              ELSE '0';
mem1write <= '1' When ((Memwrite='1') AND (wadd_bus(2 downto 0)="001"))
              ELSE '0';
mem2write <= '1' When ((Memwrite='1') AND (wadd_bus(2 downto 0)="010"))
              ELSE '0';
mem3write <= '1' When ((Memwrite='1') AND (wadd_bus(2 downto 0)="011"))
              ELSE '0';
mem4write <= '1' When ((Memwrite='1') AND (wadd_bus(2 downto 0)="100"))
              ELSE '0';
mem5write <= '1' When ((Memwrite='1') AND (wadd_bus(2 downto 0)="101"))
              ELSE '0';
mem6write <= '1' When ((Memwrite='1') AND (wadd_bus(2 downto 0)="110"))
              ELSE '0';
mem7write <= '1' When ((Memwrite='1') AND (wadd_bus(2 downto 0)="111"))
              ELSE '0';
process
begin   
wait until phi2'event and phi2='1';
   if (reset = '1') then
        mem0 <= To_stdlogicvector(X"55");
        mem1 <= To_Stdlogicvector(X"AA");
   else
   if mem0write= '1' then mem0 <= wd_bus; else mem0 <= mem0; end if;
   
   if mem1write= '1' then mem1 <= wd_bus; else mem1 <= mem1; end if;
   
   if mem2write= '1' then mem2 <= wd_bus; else mem2 <= mem2; end if;
   
   if mem3write= '1' then mem3 <= wd_bus; else mem3 <= mem3; end if;
   
   if mem4write= '1' then mem4 <= wd_bus; else mem4 <= mem4; end if;
   
   if mem5write= '1' then mem5 <= wd_bus; else mem5 <= mem5; end if;
   
   if mem6write= '1' then mem6 <= wd_bus; else mem6 <= mem6; end if;
   if mem7write= '1' then mem7 <= wd_bus; else mem7 <= mem7; end if;
   end if;
end process;
end behavioral;