i2c_top.vhd

IIC的IP.这是经过验证的源代码

       Trans_IE            : in std_logic;                        -- Transmit interrupt enable from MPU
       Recieve_IE          : in std_logic;                        -- Recieve interrupt enable from MPU
       I2C_RW              : in std_logic;                        -- I2C Read/Write register
       Trans_Buffer_Empty  : in std_logic;                        -- Interrupt enable from I2C SM
       Recieve_Buffer_Full : in std_logic;
       Iack                : in std_logic;
       Iack_Clear          : out std_logic;
       INTR_L              : out std_logic);                     -- Interrupt Request to MPU
end component;

component Start_Generator 
  port(MPU_CLK       : in std_logic;                    -- MPU Clock
       Rst_L         : in std_logic;                    -- Main Reset
       Start_Enable  : in std_logic;                    -- Start Enable, activates start gen process
       SCL           : in bit;                          -- I2C Clock for f/s mode 
       SDA           : in bit;                          -- I2C data bus for f/s mode        
       SDA_EN2       : out std_logic);                  -- sda enable
end component;

component Start_Detect 
  port(MPU_CLK       : in std_logic;                    -- MPU Clock
       Rst_L         : in std_logic;                    -- Main Reset
       SCL           : in bit;                          -- I2C Clock for f/s mode 
       SDA           : in bit;                          -- I2C data bus for f/s mode        
       Start_Det     : out std_logic);                  -- start detection bit
end component;

component Stop_Generator 
  port(MPU_CLK       : in std_logic;                    -- MPU Clock
       Rst_L         : in std_logic;                    -- Main Reset
       Stop_Enable   : in std_logic;                    -- Stop Enable, activates stop gen process
       SCL           : in bit;                          -- I2C Clock for f/s mode 
       SDA           : in bit;                          -- I2C data bus for f/s mode        
       SDA_EN3       : out std_logic);                  -- sda enable
end component;

component Stop_Detect 
  port(MPU_CLK       : in std_logic;                    -- MPU Clock
       Rst_L         : in std_logic;                    -- Main Reset
       SCL           : in bit;                          -- I2C Clock for f/s mode 
       SDA           : in bit;                          -- I2C data bus for f/s mode        
       Stop_Det      : out std_logic);                  -- stop detection bit
end component;

component Delay_SDA 
  port(MPU_CLK     : in std_logic;
       Rst_L       : in std_logic;                       
       SDA_EN      : in std_logic;
       SDA_EN_Out  : out std_logic);
end component;

begin
--=======================================================================================
-- Key Register signal assignments: GO, Abort, and Mode
--=======================================================================================
I2C_GO         <= Command_Reg(7);
I2C_Abort      <= Command_Reg(6);
I2C_Mode       <= Command_Reg(4);
I2C_Addr_Size  <= Command_Reg(2);
I2C_Trans_IE   <= Command_Reg(1);
I2C_Recieve_IE <= Command_Reg(0);
I2C_RW_Bit     <= Low_Address_Reg(0);

--Status Register Assignments
I2C_Bus_Busy   <= Status_Reg(7);    
I2C_Abort_Ack  <= Status_Reg(6);    
I2C_Error      <= Status_Reg(5);  
I2C_Lost_Arb   <= Status_Reg(4);    
I2C_Done       <= Status_Reg(3);          


SDA1  <= To_bit(SDA);
SCL1  <= To_bit(SCL);

--============================================================================
--SCL, SCLH, SDA, and SDAH drivers
--============================================================================

SCL <= '0' when SCL_CK = '1' else 'Z';

SDA <= '0' when (SDA_EN_1 = '1') or (SDA_EN_2 = '1') or (SDA_EN_3 = '1') else 'Z';

abits <= A2 & A1 & A0;

MPU_to_I2C_1 : MPU_to_I2C port map
               (MPU_CLK                 => Clock,
                Rst_L                   => Reset_L,
                CS_L                    => CS_L,
                Addr_Bits               => abits, 
                RW_L                    => RW_L,
                Read_Buffer             => Read_Buffer,
                Status_Reg(4)           => I2C_Bus_Busy,
                Status_Reg(3)           => I2C_Error,
                Status_Reg(2)           => I2C_Abort_Ack,
                Status_Reg(1)           => I2C_Lost_Arb, 
                Status_Reg(0)           => I2C_Done, 
                TBE_Set                 => Trans_Buf_Empty_Set,
                RBF_Set                 => Read_Buf_Full_Set,
                Iack_Clear              => Iack_Clear,
                Go_Clear                => Go_Clear,
                Low_Address_Reg         => Low_Address_Reg,
                Byte_Count_Reg          => Byte_Count_Reg, 
                Command_Reg             => Command_Reg,
                Trans_Buffer            => Trans_Buffer,
                Trans_Buffer_Empty      => Trans_Buffer_Empty,
                Read_Buffer_Full        => Read_Buffer_Full,
                Iack                    => I2C_Iack,
                DATA => DATA);

I2C_Main_1 : I2C_Main port map
               (MPU_CLK           => Clock,
                Rst_L             => Reset_L,
                SCL               => SCL_synch,
                SDA               => SDA_synch,
                Bit_Count         => Bit_Count,
                Bit_Cnt_Flag      => Bit_Count_Flag,
                Byte_Cnt_Flag     => Byte_Count_Flag,
                Trans_Buffer      => Trans_Buffer, 
                Low_Address_Reg   => Low_Address_Reg,
                Lost_Arb          => I2C_Lost_Arb,
                Start_Det         => Start_Det_Bit,
                Stop_Det          => Stop_Det_Bit,
                Command_Reg(1)    => I2C_GO, 
                Command_Reg(0)    => I2C_Abort,
                Status_Reg(3 downto 1)  => Status_Reg(7 downto 5),
                Status_Reg(0)     => Status_Reg(3),
                Read_Buffer       => Read_Buffer,
                Bit_Cnt_EN        => Bit_Count_Enable,
                Byte_Cnt_EN       => Byte_Count_Enable,
                Start_EN          => Start_Enable,
                Stop_EN           => Stop_Enable,
                SDA_EN1           => SDA_EN_1,
                TBE_Set           => Trans_Buf_Empty_Set,
                RBF_Set           => Read_Buf_Full_Set,
                Go_Clear          => Go_Clear,
                WCS_Ack           => wcsack,
                RCS_Ack           => rcsack);


Synch_1 : Synch_Block port map
              (MPU_CLK => Clock, Rst_L => Reset_L, SCL => SCL1, SDA => SDA1,
               SCL_synch => SCL_synch, SDA_synch => SDA_synch);


I2C_Clock_Gen_1 : I2C_Clock_Generator 
                  generic map
                  (cnt_f_hi => 7,
                   cnt_s_hi => 162,--11,
                   cnt_f_lo => 14,
                   cnt_s_lo => 325)--22)
                  port map
                  (MPU_CLK => Clock,
                   Rst_L   => Reset_L, 
                   Mode    => I2C_Mode, 
                   Abort   => I2C_Abort,
                   SCL_CK  => SCL_CK);

Counter_Blk_1 : Counter_Block port map
               (MPU_CLK => Clock, 
                Rst_L   => Reset_L,
                SCL     => SCL_synch, 
                Abort   => Command_Reg(6), 
                Byte_Cnt_EN    => Byte_Count_Enable,
                Bit_Cnt_EN     => Bit_Count_Enable,
                Go             => I2C_GO,
                Byte_Count_Reg => Byte_Count_Reg, 
                Bit_Count      => Bit_Count,
                Bit_Cnt_Flag   => Bit_Count_Flag,
                Byte_Cnt_Flag  => Byte_Count_Flag); 

Arb_1 : Arbitrator port map
       (MPU_CLK  => Clock,
        Rst_L    => Reset_L, 
        SCL      => SCL_synch,
        SDA      => SDA_synch,
        SDA_EN1  => SDA_EN_1,
        SDA_EN2  => SDA_EN_2, 
        SDA_EN3  => SDA_EN_3,
        WCS_Ack  => wcsack,
        RCS_Ack  => rcsack,
        Lost_ARB => status_reg(4));

Int_Ctrl_1 : Int_Ctrl_Block port map
             (MPU_CLK              => Clock,
              RST_L                => Reset_L,
              abort                => I2C_Abort,
              Trans_IE             => I2C_Trans_IE,
              Recieve_IE           => I2C_Recieve_IE,
              I2C_RW               => I2C_RW_Bit,
              Trans_Buffer_Empty   => Trans_Buffer_Empty,
              Recieve_Buffer_Full  => Read_Buffer_Full,
              Iack                 => I2C_Iack,
              Iack_Clear           => Iack_Clear,
              INTR_L               => INTR_L);

Start_Gen_1: Start_Generator port map
             (MPU_CLK      => Clock, 
              Rst_L        => Reset_L,
              Start_Enable => Start_Enable,
              SCL          => SCL_synch, 
              SDA          => SDA_synch,
              SDA_EN2      => SDA_EN_2);

Start_Det_1: Start_Detect port map
             (MPU_CLK   => Clock, 
              Rst_L     => Reset_L, 
              SCL       => SCL_synch,
              SDA       => SDA_synch,
              Start_Det => Start_Det_Bit);

Stop_Gen_1: Stop_Generator port map
             (MPU_CLK      => Clock, 
              Rst_L        => Reset_L,
              Stop_Enable  => Stop_Enable,
              SCL          => SCL_synch, 
              SDA          => SDA_synch,
              SDA_EN3      => SDA_EN_3);

Stop_Det_1: Stop_Detect port map
             (MPU_CLK   => Clock, 
              Rst_L     => Reset_L, 
              SCL       => SCL_synch,
              SDA       => SDA_synch,
              Stop_Det  => Stop_Det_Bit);

delay_1: Delay_SDA port map
         (MPU_CLK    => Clock,
          Rst_L      => Reset_L,
          SDA_EN     => SDA_EN_1,
          SDA_EN_Out => SDA_EN_1_out);

delay_2: Delay_SDA port map
         (MPU_CLK    => Clock,
          Rst_L      => Reset_L,
          SDA_EN     => SDA_EN_2,
          SDA_EN_Out => SDA_EN_2_out);

delay_3: Delay_SDA port map
         (MPU_CLK    => Clock,
          Rst_L      => Reset_L,
          SDA_EN     => SDA_EN_3,
          SDA_EN_Out => SDA_EN_3_out);
end behave;

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