up_model.vhd

IIC的IP.这是经过验证的源代码

------------------------------------------------------------------------------
-- 
--  Name:  up_model.vhd  
-- 
--  Description:  Emulate microprocessor transactions to the I2C master
-- 
--  $Revision: 1.0 $          
--  
--  Copyright 2004 Lattice Semiconductor Corporation.  All rights reserved.
--
------------------------------------------------------------------------------
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
------------------------------------------------------------------------------
--
--    Lattice Semiconductor Corporation
--    5555 NE Moore Court
--    Hillsboro, OR 97124
--    U.S.A
--
--    TEL: 1-800-Lattice (USA and Canada)
--    408-826-6000 (other locations)
--
--    web: http://www.latticesemi.com/
--    email: [e-mail]
-- 
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned."-";
use ieee.std_logic_unsigned."+";
use ieee.std_logic_textio.all;         
use std.textio.all;                    
use ieee.numeric_std.all;              

 
entity up_model is port(clk     : in std_logic;
                        reset_l : in std_logic;
                        ack_l   : in std_logic;
                        intr_l  : in std_logic;
                        rw_l    : out std_logic;
                        cs_l    : out std_logic;
                        addr    : out std_logic_vector(2 downto 0);
                        data    : inout std_logic_vector(7 downto 0));
end up_model;


architecture behave of up_model is              

-- --------------------------------------------------------------------
-- Constants

-- defining the address map as constants
constant data_buf      : std_logic_vector(2 downto 0) := "000";
constant low_addr      : std_logic_vector(2 downto 0) := "001";
constant upper_addr    : std_logic_vector(2 downto 0) := "010";
constant master_code   : std_logic_vector(2 downto 0) := "011";
constant comm_stat     : std_logic_vector(2 downto 0) := "100";
constant byte_count    : std_logic_vector(2 downto 0) := "101";
constant iack_reg      : std_logic_vector(2 downto 0) := "110";


-----------------------------------------------------------------------
-- reg declarations
signal data_ret : std_logic_vector(7 downto 0) := "00000000";
signal cntr     : std_logic_vector(7 downto 0) := "00000000";
signal cntr2    : std_logic_vector(13 downto 0) := "00000000000000";
signal cntr3    : std_logic_vector(13 downto 0) := "00000000000000";
signal not_used : std_logic_vector(7 downto 0):= "00000000";
signal data_out : std_logic_vector(7 downto 0):= "00000000";
------------------------------------------
-- variables

signal num_errors : integer:= 0;
signal int_flag   : integer:= 0; 
signal empty_flag : integer:= 0;  
signal done_flag  : integer:= 0; 
signal full_flag  : integer:= 0; 
signal RWL        : std_logic:= '0'; -- intermediate rw_l signal for tristate problem



begin
-----------------------------------------------------------------------
-- tri-state buffer for data bus
rw_l <= RWL;
data <= data_out when RWL = '0' else "ZZZZZZZZ";
--data <= data_out when RWL = '0' else "HHHHHHHH";
---------------------------------------------------------------------------

--//    Module  up_model
--// This module provides micro processor transactions to the I2C Master.
--// It is the stimulus control block for the top level simulation.


--init 2;
-------------------------------------------------------------------------
-- Initial Block to call uP tasks
-- These tasks read and write the appropriate data to the I2C master
-- This is the heart of the simulation because all tests are called from
-- here
--procedure init2 is
init2 : process

--//-------------------------------------------------------------------------
--// error_check

procedure error_check is
 variable L : line;
  begin 
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" Simulation complete with "));
    write(L, num_errors);
    write(L, string'(" errors. "));
    writeline(output,L);   

end error_check; 

--//--------------------------------------------------------------------------
--// kill_time
procedure kill_time is
begin 
  
  wait until rising_edge(clk);
  wait until rising_edge(clk);
  wait until rising_edge(clk);
  wait until rising_edge(clk);
    
  
end kill_time;


--// -----------------------------------------------------------------------
--// Define the uP Tasks
--// ----------------------------------------------------------------------
--// write_data_buf
procedure write_data_buf
          (data_in   : in std_logic_vector(7 downto 0)) is
 variable L : line;
 begin 
  kill_time;
  wait until rising_edge(clk);
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L,string'(" Writing Data Buf "));
    write(L, data_in);
    writeline(output,L);   

    addr <= data_buf;  
    RWL <= '0';
    data_out <= data_in;  
  wait until rising_edge(clk);
    cs_l     <= '0';
  wait until ack_l = '0';
  wait until rising_edge(clk);
    cs_l     <= '1';
  wait until rising_edge(clk);
    RWL  <= '1';
end write_data_buf;
  

--// ----------------------------------------------------------------------
--// read_data_buf

procedure read_data_buf
          (expected   : in std_logic_vector(7 downto 0);
           signal data_back  : out std_logic_vector(7 downto 0)) is
 variable L : line;
 begin 
  kill_time;
  wait until rising_edge(clk);
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L,string'(" Reading Data Buf Reg "));
    writeline(output,L);   
    addr  <= data_buf;
    RWL <= '1'; 
  wait until rising_edge(clk);
    cs_l     <= '0';
  wait until ack_l = '0';
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" Read Data "));
    write(L, data);
    writeline(output,L);   

    data_back <= data; --// The value returned from the task
  wait until rising_edge(clk);
    cs_l  <= '1';
    RWL  <= '1'; 
 
    if (data /= expected) then 
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" ERROR: data returned = "));
    write(L, data);
    write(L, string'(" data_expected = "));
    write(L, expected);
    writeline(output,L);   
     num_errors <= num_errors + 1; 
    end if;

end read_data_buf;   
  




--// ----------------------------------------------------------------------
--// write_low_add

procedure write_low_add
          (addr_in  : in std_logic_vector(7 downto 0)) is
 variable L : line;
 begin
  kill_time;
  wait until rising_edge(clk);
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" Writing Low Addr Reg "));
    write(L, addr_in);
    writeline(output,L);   

    addr <= low_addr;  
    RWL <= '0';
    data_out <= addr_in;  
  wait until rising_edge(clk);
    cs_l     <= '0';
  wait until ack_l = '0';
  wait until rising_edge(clk);
    cs_l     <= '1';
  wait until rising_edge(clk);
    RWL     <= '1';

end write_low_add;  

--// ----------------------------------------------------------------------
--// write_upper_add
procedure write_upper_add
          (addr_in : in std_logic_vector(7 downto 0)) is
 variable L : line;
 begin 
  kill_time;   
  wait until rising_edge(clk);
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" Writing Upper Addr Reg "));
    write(L, addr_in);
    writeline(output,L);   

    addr <= upper_addr;  
    RWL <= '0';
    data_out <= addr_in;  
  wait until rising_edge(clk);
    cs_l     <= '0';
  wait until ack_l = '0';
  wait until rising_edge(clk);
    cs_l     <= '1';
  wait until rising_edge(clk);
    RWL  <= '1';

end write_upper_add; 



--// ----------------------------------------------------------------------
--// write_master_code
procedure write_master_code
          (data_in : in std_logic_vector(7 downto 0)) is
 variable L : line;
 begin 
  kill_time;
  wait until rising_edge(clk);
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" Writing Master Code Reg "));
    write(L, data_in);
    writeline(output,L);   

    addr <= master_code;  
    RWL <= '0';
    data_out <= data_in;  
  wait until rising_edge(clk);
    cs_l     <= '0';
  wait until ack_l = '0';
  wait until rising_edge(clk);
    cs_l     <= '1';
  wait until rising_edge(clk);
    RWL  <= '1';
end write_master_code;
  


--// ----------------------------------------------------------------------
--// write_command_reg
procedure write_command_reg
          (data_in : in std_logic_vector(7 downto 0)) is
 variable L : line;
 begin 
  kill_time;   
  wait until rising_edge(clk);
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" Writing Command Reg "));
    write(L, data_in);
    writeline(output,L);   

    addr <= comm_stat;  
    RWL <= '0';
    data_out <= data_in;  
  wait until rising_edge(clk);
    cs_l     <= '0';
  wait until ack_l = '0';
  wait until rising_edge(clk);
    cs_l     <= '1';
  wait until rising_edge(clk);
    RWL  <= '1';

end write_command_reg;



--// ----------------------------------------------------------------------
--// read_status_reg
procedure read_status_reg
          (debug : in std_logic;
           signal data_back : out std_logic_vector(7 downto 0)) is --// pass a 1 to turn debug on & a 0 to turn it off
 variable L : line;
 begin 
  kill_time;
  wait until rising_edge(clk);
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" Reading Status Reg "));
    writeline(output,L);   

  addr  <= comm_stat;
  RWL  <= '1'; 
  wait until rising_edge(clk);
    cs_l  <= '0';
  wait until ack_l = '0';
  if (debug = '1') then
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" uP Read Data "));
    write(L, data);
    writeline(output,L);   

  end if;
  data_back <= data; --// The value returned from the task
    wait until rising_edge(clk);
    cs_l  <= '1';
    RWL  <= '1'; 
 
end read_status_reg;
 
--//--------------------------------------------------------------------------
--// check_done task
procedure check_done is
   variable L : line;
  begin 
  
  -- check for done bit before continuing
  
 
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" Checking the done bit "));
    writeline(output,L);   

  -- initialize some variables
   cntr <= "00000000";
   done_flag <= 0;
   
   -- start checking status
   while (cntr /= "11111111" and done_flag = 0) loop 
     wait until rising_edge(clk);
     wait until rising_edge(clk);
     -- read the status
     read_status_reg('0',data_ret);
      
     if (data_ret(3) = '1') then 
     -- we have the done bit so set the done flag
       done_flag <= 1;
     else 
     -- status says not done
        cntr <= cntr + 1;
     end if;
   end loop; -- end of while

   if (cntr = "11111111") then 
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" ERROR cntr expired waiting for Done Flag!"));
    writeline(output,L);   

     num_errors <= num_errors + 1;
   end if;  
 
end check_done;



--// ----------------------------------------------------------------------
--// write_byte_count
procedure write_byte_count 
          (data_in : std_logic_vector(7 downto 0)) is
 variable L : line;
 begin
  kill_time;
  wait until rising_edge(clk);
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" Writing Byte Count "));
    write(L, data_in);
    writeline(output,L);   

    addr <= byte_count;  
    RWL <= '0';
    data_out <= data_in;  
  wait until rising_edge(clk);
    cs_l     <= '0';
  wait until ack_l = '0';
  wait until rising_edge(clk);
    cs_l     <= '1';
  wait until rising_edge(clk);
    RWL  <= '1';
  
end write_byte_count;



--// ----------------------------------------------------------------------
--// clear_iack
procedure clear_iack is
 variable L : line;
begin
  kill_time;
  wait until rising_edge(clk);
    write(L,now, justified => right, field=>10,unit=>ns);
    write(L, string'(" Clearing Iack Reg "));
    writeline(output,L);   

    addr <= iack_reg;  
    RWL <= '0';
    data_out <= "00000000";  
  wait until rising_edge(clk);