📄 4、分频器源程序divider:.txt
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE P_ALARM IS
SUBTYPE T_DIGITAL IS INTEGER RANGE 0 TO 9;
SUBTYPE T_SHORT IS INTEGER RANGE 0 TO 65535;
TYPE T_CLOCK_TIME IS ARRAY (5 DOWNTO 0) OF T_DIGITAL;
TYPE T_DISPLAY IS ARRAY (5 DOWNTO 0) OF T_DIGITAL;
END PACKAGE P_ALARM;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.P_ALARM.ALL;
ENTITY DIVIDER IS
PORT(CLK_IN: IN STD_LOGIC;
RESET: IN STD_LOGIC;
CLK_OUT: OUT STD_LOGIC);
END DIVIDER;
ARCHITECTURE ART OF DIVIDER IS
CONSTANT DIVIDE_PERIOD: T_SHORT:=6000;
BEGIN
DIVIDE_CLK: PROCESS(CLK_IN,RESET)IS
VARIABLE CNT: T_SHORT;
BEGIN
IF(RESET='1') THEN
CNT:=0;
CLK_OUT<='0';
ELSIF RISING_EDGE(CLK_IN) THEN
IF(CNT<(DIVIDE_PERIOD/2) )THEN
CLK_OUT<='1';
CNT:=CNT+1;
ELSIF(CNT<(DIVIDE_PERIOD-1)) THEN
CLK_OUT<='0';
CNT:=CNT+1;
ELSE
CNT:=0;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART;
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