song.syr

自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

# BELS                             : 196
#      GND                         : 1
#      LUT1                        : 6
#      LUT1_D                      : 1
#      LUT1_L                      : 1
#      LUT2                        : 4
#      LUT3                        : 23
#      LUT3_L                      : 12
#      LUT4                        : 73
#      LUT4_D                      : 2
#      LUT4_L                      : 2
#      MUXCY                       : 20
#      MUXF5                       : 20
#      MUXF6                       : 10
#      VCC                         : 1
#      XORCY                       : 20
# FlipFlops/Latches                : 32
#      FD                          : 1
#      FDE                         : 13
#      FDR                         : 18
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 13
#      OBUF                        : 13
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      74  out of    768     9%  
 Number of Slice Flip Flops:            32  out of   1536     2%  
 Number of 4 input LUTs:               124  out of   1536     8%  
 Number of bonded IOBs:                 13  out of     96    13%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk4m                              | BUFGP                  | 14    |
carrier:Q                          | NONE                   | 3     |
clk4                               | BUFGP                  | 15    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.644ns (Maximum Frequency: 103.691MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 16.266ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk4m'
Delay:               9.644ns (Levels of Logic = 16)
  Source:            divider_0 (FF)
  Destination:       divider_12 (FF)
  Source Clock:      clk4m rising
  Destination Clock: clk4m rising

  Data Path: divider_0 to divider_12
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.085   1.206  divider_0 (divider_0)
     LUT4:I0->O            2   0.549   1.206  _n000417 (CHOICE527)
     LUT4_D:I1->O         13   0.549   2.250  _n000427 (_n0004)
     LUT3_L:I0->LO         1   0.549   0.000  divider_inst_lut3_01 (divider_inst_lut3_0)
     MUXCY:S->O            1   0.659   0.000  divider_inst_cy_1 (divider_inst_cy_1)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_2 (divider_inst_cy_2)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_3 (divider_inst_cy_3)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_4 (divider_inst_cy_4)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_5 (divider_inst_cy_5)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_6 (divider_inst_cy_6)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_7 (divider_inst_cy_7)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_8 (divider_inst_cy_8)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_9 (divider_inst_cy_9)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_10 (divider_inst_cy_10)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_11 (divider_inst_cy_11)
     MUXCY:CI->O           0   0.042   0.000  divider_inst_cy_12 (divider_inst_cy_12)
     XORCY:CI->O           1   0.420   0.000  divider_inst_sum_12 (divider_inst_sum_12)
     FDE:D                     0.709          divider_12
    ----------------------------------------
    Total                      9.644ns (4.982ns logic, 4.662ns route)
                                       (51.7% logic, 48.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'carrier:Q'
Delay:               4.735ns (Levels of Logic = 1)
  Source:            count_0 (FF)
  Destination:       speaker (FF)
  Source Clock:      carrier:Q rising
  Destination Clock: carrier:Q rising

  Data Path: count_0 to speaker
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   1.085   1.332  count_0 (count_0)
     LUT2:I0->O            1   0.549   1.035  _n00431 (_n0043)
     FDR:R                     0.734          speaker
    ----------------------------------------
    Total                      4.735ns (2.368ns logic, 2.367ns route)
                                       (50.0% logic, 50.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk4'
Delay:               8.057ns (Levels of Logic = 2)
  Source:            counter_5 (FF)
  Destination:       counter_6 (FF)
  Source Clock:      clk4 rising
  Destination Clock: clk4 rising

  Data Path: counter_5 to counter_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             17   1.085   2.610  counter_5 (counter_5)
     LUT4_L:I2->LO         1   0.549   0.100  _n000620 (CHOICE516)
     LUT2:I1->O           15   0.549   2.430  _n000621 (_n0006)
     FDR:R                     0.734          counter_0
    ----------------------------------------
    Total                      8.057ns (2.917ns logic, 5.140ns route)
                                       (36.2% logic, 63.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'carrier:Q'
Offset:              6.788ns (Levels of Logic = 1)
  Source:            speaker (FF)
  Destination:       speaker (PAD)
  Source Clock:      carrier:Q rising

  Data Path: speaker to speaker
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   1.085   1.035  speaker (speaker_OBUF)
     OBUF:I->O                 4.668          speaker_OBUF (speaker)
    ----------------------------------------
    Total                      6.788ns (5.753ns logic, 1.035ns route)
                                       (84.8% logic, 15.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk4'
Offset:              16.266ns (Levels of Logic = 6)
  Source:            counter_3_2 (FF)
  Destination:       digit<0> (PAD)
  Source Clock:      clk4 rising

  Data Path: counter_3_2 to digit<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             39   1.085   3.735  counter_3_2 (counter_3_2)
     LUT4:I3->O            1   0.549   0.000  Mrom_digit_inst_lut4_01 (Mrom_digit_inst_lut4_0)
     MUXF5:I0->O           1   0.315   0.000  Mrom_digit_inst_mux_f5_0 (Mrom_digit__net1)
     MUXF6:I0->O           1   0.316   1.035  Mrom_digit_inst_mux_f6_0 (Mrom_digit__net3)
     LUT3:I2->O            1   0.549   1.035  Mrom_digit_inst_mux_f5_5_SW0 (N6472)
     LUT4:I3->O           15   0.549   2.430  Mrom_digit_inst_mux_f5_5 (digit_0_OBUF)
     OBUF:I->O                 4.668          digit_0_OBUF (digit<0>)
    ----------------------------------------
    Total                     16.266ns (8.031ns logic, 8.235ns route)
                                       (49.4% logic, 50.6% route)

=========================================================================
CPU : 8.60 / 10.64 s | Elapsed : 9.00 / 11.00 s
 
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Total memory usage is 73336 kilobytes