song.syr

自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的歌曲

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: song.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : song.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : song
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : song
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : song.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/dragon/VHDL/lzhu/song.vhdl in Library work.
Entity <song> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <song> (Architecture <Behavioral>).
INFO:Xst:1739 - HDL ADVISOR - F:/dragon/VHDL/lzhu/song.vhdl line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
WARNING:Xst:819 - F:/dragon/VHDL/lzhu/song.vhdl line 48: The following signals are missing in the process sensitivity list:
   counter.
Entity <song> analyzed. Unit <song> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <song>.
    Related source file is F:/dragon/VHDL/lzhu/song.vhdl.
    Found 256x7-bit ROM for signal <digit>.
    Found 1-bit register for signal <speaker>.
    Found 1-bit register for signal <carrier>.
    Found 2-bit up counter for signal <count>.
    Found 8-bit up counter for signal <counter>.
    Found 13-bit up counter for signal <divider>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <song> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 256x7-bit ROM                     : 1
# Counters                         : 3
 13-bit up counter                 : 1
 8-bit up counter                  : 1
 2-bit up counter                  : 1
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <song> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block song, actual ratio is 9.
FlipFlop counter_3 has been replicated 1 time(s)
FlipFlop counter_2 has been replicated 1 time(s)
FlipFlop counter_1 has been replicated 1 time(s)
FlipFlop counter_0 has been replicated 1 time(s)
FlipFlop counter_4 has been replicated 1 time(s)
FlipFlop counter_3 has been replicated 1 time(s)
FlipFlop counter_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : song.ngr
Top Level Output File Name         : song
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 15

Macro Statistics :
# ROMs                             : 1
#      256x7-bit ROM               : 1
# Registers                        : 4
#      1-bit register              : 2
#      2-bit register              : 2
# Counters                         : 1
#      13-bit up counter           : 1

Cell Usage :