_primary.vhd

来自「布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity maxii_mux21 is
    port(
        MO              : out    vl_logic;
        A               : in     vl_logic;
        B               : in     vl_logic;
        S               : in     vl_logic
    );
end maxii_mux21;