booth_pipeline.vif

来自「布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.」· VIF 代码 · 共 54 行

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  booth_pipeline.vlf

# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Altera

# RTL and technology files
vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -original -verilog ../../src/booth_pipeline.v
vif_set_top_module -original -top booth_pipeline
 
vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -translated -verilog booth_pipeline.vqm
vif_set_top_module -translated -top booth_pipeline 
# Read FSM encoding

# Memory map points

# SRL map points

# Compiler constant registers

# Compiler constant latches

# Compiler RTL sequential redundancies

# RTL sequential redundancies

# Technology sequential redundancies

# Inversion map points

# Port mappping and directions

# Black box mapping


# Other sequential cells, including multidimensional arrays

# Constant Registers

# Retimed Registers

# Altera MAC annotations