_primary.vhd

来自「布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity cyclone_routing_wire is
    port(
        datain          : in     vl_logic;
        dataout         : out    vl_logic
    );
end cyclone_routing_wire;