_primary.vhd

来自「布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity booth_com is
    generic(
        N               : integer := 4
    );
    port(
        PRO             : out    vl_logic_vector;
        \RST_\          : in     vl_logic;
        CLK             : in     vl_logic;
        M1              : in     vl_logic_vector;
        M2              : in     vl_logic_vector
    );
end booth_com;