_primary.vhd

来自「布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity booth_pipeline is
    port(
        CLK             : in     vl_logic;
        \RST_\          : in     vl_logic;
        M2              : in     vl_logic_vector(3 downto 0);
        M1              : in     vl_logic_vector(3 downto 0);
        PRO             : out    vl_logic_vector(7 downto 0)
    );
end booth_pipeline;