booth_com.map.qmsg

布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 05 21:37:49 2006 " "Info: Processing started: Tue Sep 05 21:37:49 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off booth_com -c booth_com " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off booth_com -c booth_com" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../src/booth_com.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../src/booth_com.v" { { "Info" "ISGN_ENTITY_NAME" "1 booth_com " "Info: Found entity 1: booth_com" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "booth_com " "Info: Elaborating entity \"booth_com\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 booth_com.v(49) " "Warning: Verilog HDL assignment warning at booth_com.v(49): truncated value with size 32 to match size of target (4)" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 booth_com.v(55) " "Warning: Verilog HDL assignment warning at booth_com.v(55): truncated value with size 32 to match size of target (4)" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 55 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 booth_com.v(67) " "Warning: Verilog HDL assignment warning at booth_com.v(67): truncated value with size 32 to match size of target (1)" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 67 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 booth_com.v(68) " "Warning: Verilog HDL assignment warning at booth_com.v(68): truncated value with size 32 to match size of target (4)" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 68 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_CONDITION_REDUNDANT" "booth_com.v(79) " "Warning: Verilog HDL Case Statement warning at booth_com.v(79): case item expression is ignored because it never applies" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 79 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_CONDITION_REDUNDANT" "booth_com.v(93) " "Warning: Verilog HDL Case Statement warning at booth_com.v(93): case item expression is ignored because it never applies" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 93 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 booth_com.v(101) " "Warning: Verilog HDL assignment warning at booth_com.v(101): truncated value with size 32 to match size of target (4)" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 101 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 booth_com.v(102) " "Warning: Verilog HDL assignment warning at booth_com.v(102): truncated value with size 32 to match size of target (4)" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 102 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 booth_com.v(113) " "Warning: Verilog HDL assignment warning at booth_com.v(113): truncated value with size 32 to match size of target (8)" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 113 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 booth_com.v(115) " "Warning: Verilog HDL assignment warning at booth_com.v(115): truncated value with size 32 to match size of target (8)" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 115 0 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "pro_reg\[6\] pro_reg\[7\] " "Info: Duplicate register \"pro_reg\[6\]\" merged to single register \"pro_reg\[7\]\"" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "75 " "Info: Implemented 75 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "57 " "Info: Implemented 57 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 05 21:37:52 2006 " "Info: Processing ended: Tue Sep 05 21:37:52 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}