booth_pipeline.fit.qmsg

布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "16 unused 3.30 8 8 0 " "Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 8 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 2 36 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  36 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.826 ns register pin " "Info: Estimated most critical path is register to pin delay of 1.826 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pro_reg\[3\] 1 REG LAB_X2_Y2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y2; Fanout = 1; REG Node = 'pro_reg\[3\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "" { pro_reg[3] } "NODE_NAME" } "" } } { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 61 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(1.454 ns) 1.826 ns PRO\[3\] 2 PIN PIN_16 0 " "Info: 2: + IC(0.372 ns) + CELL(1.454 ns) = 1.826 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'PRO\[3\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "1.826 ns" { pro_reg[3] PRO[3] } "NODE_NAME" } "" } } { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns 79.63 % " "Info: Total cell delay = 1.454 ns ( 79.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.372 ns 20.37 % " "Info: Total interconnect delay = 0.372 ns ( 20.37 % )" {  } {  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "1.826 ns" { pro_reg[3] PRO[3] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 05 22:02:44 2006 " "Info: Processing ended: Tue Sep 05 22:02:44 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}