booth_pipeline.map.qmsg

布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 05 22:02:32 2006 " "Info: Processing started: Tue Sep 05 22:02:32 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off booth_pipeline -c booth_pipeline " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off booth_pipeline -c booth_pipeline" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../src/booth_pipeline.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../src/booth_pipeline.v" { { "Info" "ISGN_ENTITY_NAME" "1 booth_pipeline " "Info: Found entity 1: booth_pipeline" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "booth_pipeline " "Info: Elaborating entity \"booth_pipeline\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_CASE_CONDITION_REDUNDANT" "booth_pipeline.v(84) " "Warning: Verilog HDL Case Statement warning at booth_pipeline.v(84): case item expression is ignored because it never applies" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 84 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "booth_pipeline.v(119) " "Info: Verilog HDL Case Statement information at booth_pipeline.v(119): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 119 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "booth_pipeline.v(155) " "Info: Verilog HDL Case Statement information at booth_pipeline.v(155): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 155 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "booth_pipeline.v(191) " "Info: Verilog HDL Case Statement information at booth_pipeline.v(191): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 191 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 booth_pipeline.v(198) " "Warning: Verilog HDL assignment warning at booth_pipeline.v(198): truncated value with size 4 to match size of target (1)" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 198 0 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "pro_tmp_st1\[2\] pro_tmp_st1\[3\] " "Info: Duplicate register \"pro_tmp_st1\[2\]\" merged to single register \"pro_tmp_st1\[3\]\"" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 50 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pro_tmp_st2\[2\] pro_tmp_st2\[3\] " "Info: Duplicate register \"pro_tmp_st2\[2\]\" merged to single register \"pro_tmp_st2\[3\]\"" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 51 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pro_tmp_st3\[2\] pro_tmp_st3\[3\] " "Info: Duplicate register \"pro_tmp_st3\[2\]\" merged to single register \"pro_tmp_st3\[3\]\"" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 52 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pro_tmp_st4\[2\] pro_tmp_st4\[3\] " "Info: Duplicate register \"pro_tmp_st4\[2\]\" merged to single register \"pro_tmp_st4\[3\]\"" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 53 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pro_reg\[6\] pro_reg\[7\] " "Info: Duplicate register \"pro_reg\[6\]\" merged to single register \"pro_reg\[7\]\"" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 61 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "99 " "Info: Implemented 99 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "81 " "Info: Implemented 81 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 05 22:02:35 2006 " "Info: Processing ended: Tue Sep 05 22:02:35 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}