booth_pipeline.vo

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// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "09/05/2006 22:03:07"

// 
// Device: Altera EPM240T100C3 Package TQFP100
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	booth_pipeline (
	CLK,
	RST_,
	M2,
	M1,
	PRO);
input 	CLK;
input 	RST_;
input 	[3:0] M2;
input 	[3:0] M1;
output 	[7:0] PRO;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("booth_pipeline_v.sdo");
// synopsys translate_on

wire \m2_tmp_st3[0] ;
wire \m1_tmp_st4[3]~67 ;
wire \m2_tmp_st3[1] ;
wire \m2_tmp_st3[2] ;
wire \m2_tmp_st3[3] ;
wire \m1_tmp_st3[3]~66 ;
wire \m1_tmp_st2[3]~66 ;
wire \CLK~combout ;
wire \M1[1]~combout ;
wire \RST_~combout ;
wire \m1_reg[1] ;
wire \M1[2]~combout ;
wire \m1_reg[2] ;
wire \M2[1]~combout ;
wire \m2_reg[1] ;
wire \M2[0]~combout ;
wire \M2[2]~combout ;
wire \m2_reg[2] ;
wire \m2_reg[1]~52 ;
wire \M1[0]~combout ;
wire \m1_reg[0] ;
wire zero_st1;
wire \m2_reg[0] ;
wire \m1_tmp_st1[3] ;
wire \m1_tmp_st2[2] ;
wire zero_st2;
wire \m1_tmp_st3[1] ;
wire zero_st3;
wire \m1_tmp_st4[0] ;
wire \pro_reg[0] ;
wire \always2~0 ;
wire \pro_tmp_st1[0] ;
wire \m1_tmp_st1[0] ;
wire aid_st1;
wire \add~883 ;
wire \par_st2~35 ;
wire \m1_tmp_st2[3]~66COUT0_76 ;
wire \m1_tmp_st2[3]~66COUT1_77 ;
wire \m1_tmp_st2[3] ;
wire \m1_tmp_st3[2] ;
wire \m1_tmp_st4[1] ;
wire \pro_reg[1] ;
wire \m1_tmp_st1[1] ;
wire \m1_tmp_st2[0] ;
wire aid_st2;
wire \m2_tmp_st1[0] ;
wire \add~879 ;
wire \pro_tmp_st1[1] ;
wire \add~884 ;
wire \m1_tmp_st2[3]~60 ;
wire \m1_tmp_st2[3]~60COUT1_78 ;
wire \pro_tmp_st2[0] ;
wire \par_st3~35 ;
wire \m1_tmp_st3[3]~66COUT0_75 ;
wire \m1_tmp_st3[3]~66COUT1_76 ;
wire \m1_tmp_st3[3] ;
wire \m1_tmp_st4[2] ;
wire \pro_reg[2] ;
wire \add~885 ;
wire \M2[3]~combout ;
wire \m2_reg[3] ;
wire \pro_tmp_st1[3] ;
wire \pro_tmp_st2[0]~47 ;
wire \pro_tmp_st2[0]~47COUT1_62 ;
wire \pro_tmp_st2[1] ;
wire \m2_tmp_st1[1] ;
wire \add~880 ;
wire \m1_tmp_st3[3]~59 ;
wire \m1_tmp_st3[3]~59COUT1_77 ;
wire \pro_tmp_st3[0] ;
wire \M1[3]~combout ;
wire \m1_reg[3] ;
wire \m1_tmp_st1[2] ;
wire \m1_tmp_st2[1] ;
wire \m1_tmp_st3[0] ;
wire aid_st3;
wire \m2_tmp_st2[0] ;
wire \add~875 ;
wire \par_st4~35 ;
wire \m1_tmp_st4[3]~67COUT0_75 ;
wire \m1_tmp_st4[3]~67COUT1_76 ;
wire \m1_tmp_st4[3] ;
wire \pro_reg[3] ;
wire \add~886 ;
wire \pro_tmp_st2[1]~51 ;
wire \pro_tmp_st2[1]~51COUT1_64 ;
wire \pro_tmp_st2[3] ;
wire \m2_tmp_st1[2] ;
wire \add~881 ;
wire \pro_tmp_st3[0]~48 ;
wire \pro_tmp_st3[0]~48COUT1_63 ;
wire \pro_tmp_st3[1] ;
wire \m2_tmp_st2[1] ;
wire \add~876 ;
wire \m1_tmp_st4[3]~59 ;
wire \m1_tmp_st4[3]~59COUT1_77 ;
wire \pro_tmp_st4[0] ;
wire \pro_reg[4] ;
wire \m2_tmp_st2[2] ;
wire \add~877 ;
wire \m2_tmp_st1[3] ;
wire \add~882 ;
wire \pro_tmp_st3[1]~52 ;
wire \pro_tmp_st3[1]~52COUT1_65 ;
wire \pro_tmp_st3[3] ;
wire \pro_tmp_st4[0]~48 ;
wire \pro_tmp_st4[0]~48COUT1_63 ;
wire \pro_tmp_st4[1] ;
wire \pro_reg[5] ;
wire \m2_tmp_st2[3] ;
wire \add~878 ;
wire \pro_tmp_st4[1]~52 ;
wire \pro_tmp_st4[1]~52COUT1_65 ;
wire \pro_tmp_st4[3] ;
wire \pro_reg[7] ;


// atom is at PIN_14
maxii_io \CLK~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\CLK~combout ),
	.padio(CLK));
// synopsys translate_off
defparam \CLK~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_2
maxii_io \M1[1]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M1[1]~combout ),
	.padio(M1[1]));
// synopsys translate_off
defparam \M1[1]~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_12
maxii_io \RST_~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RST_~combout ),
	.padio(RST_));
// synopsys translate_off
defparam \RST_~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X2_Y4_N5
maxii_lcell \m1_reg[1]~I (
// Equation(s):
// \m1_reg[1]  = DFFEAS(\M1[1]~combout , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , , , , )

	.clk(\CLK~combout ),
	.dataa(vcc),
	.datab(\M1[1]~combout ),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\RST_~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\m1_reg[1] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \m1_reg[1]~I .operation_mode = "normal";
defparam \m1_reg[1]~I .synch_mode = "off";
defparam \m1_reg[1]~I .register_cascade_mode = "off";
defparam \m1_reg[1]~I .sum_lutc_input = "datac";
defparam \m1_reg[1]~I .lut_mask = "CCCC";
defparam \m1_reg[1]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at PIN_52
maxii_io \M1[2]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M1[2]~combout ),
	.padio(M1[2]));
// synopsys translate_off
defparam \M1[2]~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X7_Y1_N1
maxii_lcell \m1_reg[2]~I (
// Equation(s):
// \m1_reg[2]  = DFFEAS(\M1[2]~combout , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , , , , )

	.clk(\CLK~combout ),
	.dataa(\M1[2]~combout ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\RST_~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\m1_reg[2] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \m1_reg[2]~I .operation_mode = "normal";
defparam \m1_reg[2]~I .synch_mode = "off";
defparam \m1_reg[2]~I .register_cascade_mode = "off";
defparam \m1_reg[2]~I .sum_lutc_input = "datac";
defparam \m1_reg[2]~I .lut_mask = "AAAA";
defparam \m1_reg[2]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at PIN_62
maxii_io \M2[1]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M2[1]~combout ),
	.padio(M2[1]));
// synopsys translate_off
defparam \M2[1]~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X5_Y2_N0
maxii_lcell \m2_reg[1]~I (
// Equation(s):
// \m2_reg[1]  = DFFEAS(\M2[1]~combout , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , , , , )

	.clk(\CLK~combout ),
	.dataa(\M2[1]~combout ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\RST_~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\m2_reg[1] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \m2_reg[1]~I .operation_mode = "normal";
defparam \m2_reg[1]~I .synch_mode = "off";
defparam \m2_reg[1]~I .register_cascade_mode = "off";
defparam \m2_reg[1]~I .sum_lutc_input = "datac";
defparam \m2_reg[1]~I .lut_mask = "AAAA";
defparam \m2_reg[1]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at PIN_42
maxii_io \M2[0]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M2[0]~combout ),
	.padio(M2[0]));
// synopsys translate_off
defparam \M2[0]~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_61
maxii_io \M2[2]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M2[2]~combout ),
	.padio(M2[2]));
// synopsys translate_off
defparam \M2[2]~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X6_Y2_N4
maxii_lcell \m2_reg[2]~I (
// Equation(s):
// \m2_reg[2]  = DFFEAS(\M2[2]~combout , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , , , , )

	.clk(\CLK~combout ),
	.dataa(\M2[2]~combout ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\RST_~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\m2_reg[2] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \m2_reg[2]~I .operation_mode = "normal";
defparam \m2_reg[2]~I .synch_mode = "off";
defparam \m2_reg[2]~I .register_cascade_mode = "off";
defparam \m2_reg[2]~I .sum_lutc_input = "datac";
defparam \m2_reg[2]~I .lut_mask = "AAAA";
defparam \m2_reg[2]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X5_Y2_N4
maxii_lcell \m2_reg[0]~I (
// Equation(s):
// \m2_reg[1]~52  = !\m2_reg[1]  & !m2_reg[0] & !\m2_reg[2] 
// \m2_reg[0]  = DFFEAS(\m2_reg[1]~52 , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , \M2[0]~combout , , , VCC)

	.clk(\CLK~combout ),
	.dataa(vcc),
	.datab(\m2_reg[1] ),
	.datac(\M2[0]~combout ),
	.datad(\m2_reg[2] ),
	.aclr(!\RST_~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\m2_reg[1]~52 ),
	.regout(\m2_reg[0] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \m2_reg[0]~I .operation_mode = "normal";
defparam \m2_reg[0]~I .synch_mode = "on";
defparam \m2_reg[0]~I .register_cascade_mode = "off";
defparam \m2_reg[0]~I .sum_lutc_input = "qfbk";
defparam \m2_reg[0]~I .lut_mask = "0003";
defparam \m2_reg[0]~I .output_mode = "reg_and_comb";
// synopsys translate_on

// atom is at PIN_73
maxii_io \M1[0]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M1[0]~combout ),
	.padio(M1[0]));
// synopsys translate_off
defparam \M1[0]~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X6_Y4_N2
maxii_lcell \m1_reg[0]~I (
// Equation(s):
// \m1_reg[0]  = DFFEAS(\M1[0]~combout , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , , , , )

	.clk(\CLK~combout ),
	.dataa(\M1[0]~combout ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\RST_~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\m1_reg[0] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \m1_reg[0]~I .operation_mode = "normal";
defparam \m1_reg[0]~I .synch_mode = "off";
defparam \m1_reg[0]~I .register_cascade_mode = "off";
defparam \m1_reg[0]~I .sum_lutc_input = "datac";
defparam \m1_reg[0]~I .lut_mask = "AAAA";
defparam \m1_reg[0]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X5_Y2_N2
maxii_lcell \zero_st1~I (
// Equation(s):
// \always2~0  = \m2_reg[1]~52  # !\m1_reg[1]  & !\m1_reg[2]  & !\m1_reg[0] 
// zero_st1 = DFFEAS(\always2~0 , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , , , , )

	.clk(\CLK~combout ),
	.dataa(\m1_reg[1] ),
	.datab(\m1_reg[2] ),