led.vhd

FPGA设计的时钟！很特别

--************************************************************************--
--七段共阴极LED数码管译码程序
--************************************************************************--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led is
port( din  : in	std_logic_vector(3 downto 0);
	  dout : out std_logic_vector(6 downto 0) );
end led;

architecture behv of led is
begin
	process( din )
	begin
		case din is
			when "0000" =>	dout<="0111111";	--0
			when "0001" =>	dout<="0000110";    --1 
			when "0010" =>	dout<="1011011";	--2
			when "0011" =>	dout<="1001111";	--3
			when "0100" =>	dout<="1100110";	--4
			when "0101" =>	dout<="1101101";	--5
			when "0110" =>	dout<="1111101";	--6
			when "0111" =>	dout<="0000111";	--7
			when "1000" =>	dout<="1111111";	--8
			when "1001" =>	dout<="1101111";	--9
			when others =>  dout<="1111001";	--e 系统报错
		end	case;
	end process;
end behv;