sec_out.vhd

来自「FPGA设计的时钟！很特别」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sec_out is
	port ( set : in std_logic;       
		   alarm  : in std_logic;      
		   sec60_0 ,sec60_1:    in std_logic_vector(3 downto 0);
           sec_set_0,sec_set_1: in std_logic_vector(3 downto 0);
           sec_a_0  , sec_a_1:  in std_logic_vector(3 downto 0);
           sec0_out , sec1_out: out std_logic_vector(3 downto 0));    
end sec_out;

architecture arch of sec_out is
	signal sec0_tmp,sec1_tmp : std_logic_vector(3 downto 0);
 begin
      process ( set,alarm) 			
       begin
         if ( set='1' ) then        
			sec0_tmp<=sec_set_0;
			sec1_tmp<=sec_set_1;
		 elsif ( alarm ='1' ) then	
			sec0_tmp<=sec_a_0;
			sec1_tmp<=sec_a_1;			
             else			       
                   sec0_tmp<= sec60_0;
			       sec1_tmp<=sec60_1;
             end if;
     end process;
	sec0_out<=sec0_tmp;
	sec1_out<=sec1_tmp;

end  architecture arch;