gather24.vhd

FPGA设计的时钟！很特别

--************************************************************************--
--拼接程序
--说明：将秒，分和时的计数器输出拼接起来，以便进行比较。
--************************************************************************--


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gather24 is
	port ( sec0,sec1   : in std_logic_vector(3 downto 0);
           min0,min1   : in std_logic_vector(3 downto 0);
		   hour0,hour1 : in std_logic_vector(3 downto 0);
		   qout : out std_logic_vector(23 downto 0) );
end gather24;

architecture arch of gather24 is
begin
	process ( min0,min1,hour0,hour1 )
	begin
		qout<=hour1&hour0&min1&min0&sec1&sec0;
	end process;
end arch;