gather24.rpt

FPGA设计的时钟！很特别

-- Node name is 'qout7' 
-- Equation name is 'qout7', type is output 
qout7    =  _LC4_B9;

-- Node name is 'qout8~1' 
-- Equation name is 'qout8~1', location is LC8_B1, type is buried.
-- synthesized logic cell 
_LC8_B1  = LCELL( min00);

-- Node name is 'qout8' 
-- Equation name is 'qout8', type is output 
qout8    =  _LC8_B1;

-- Node name is 'qout9~1' 
-- Equation name is 'qout9~1', location is LC3_C13, type is buried.
-- synthesized logic cell 
_LC3_C13 = LCELL( min01);

-- Node name is 'qout9' 
-- Equation name is 'qout9', type is output 
qout9    =  _LC3_C13;

-- Node name is 'qout10~1' 
-- Equation name is 'qout10~1', location is LC7_A2, type is buried.
-- synthesized logic cell 
_LC7_A2  = LCELL( min02);

-- Node name is 'qout10' 
-- Equation name is 'qout10', type is output 
qout10   =  _LC7_A2;

-- Node name is 'qout11~1' 
-- Equation name is 'qout11~1', location is LC1_B15, type is buried.
-- synthesized logic cell 
_LC1_B15 = LCELL( min03);

-- Node name is 'qout11' 
-- Equation name is 'qout11', type is output 
qout11   =  _LC1_B15;

-- Node name is 'qout12~1' 
-- Equation name is 'qout12~1', location is LC1_C15, type is buried.
-- synthesized logic cell 
_LC1_C15 = LCELL( min10);

-- Node name is 'qout12' 
-- Equation name is 'qout12', type is output 
qout12   =  _LC1_C15;

-- Node name is 'qout13~1' 
-- Equation name is 'qout13~1', location is LC2_C10, type is buried.
-- synthesized logic cell 
_LC2_C10 = LCELL( min11);

-- Node name is 'qout13' 
-- Equation name is 'qout13', type is output 
qout13   =  _LC2_C10;

-- Node name is 'qout14~1' 
-- Equation name is 'qout14~1', location is LC2_C2, type is buried.
-- synthesized logic cell 
_LC2_C2  = LCELL( min12);

-- Node name is 'qout14' 
-- Equation name is 'qout14', type is output 
qout14   =  _LC2_C2;

-- Node name is 'qout15~1' 
-- Equation name is 'qout15~1', location is LC1_B9, type is buried.
-- synthesized logic cell 
_LC1_B9  = LCELL( min13);

-- Node name is 'qout15' 
-- Equation name is 'qout15', type is output 
qout15   =  _LC1_B9;

-- Node name is 'qout16~1' 
-- Equation name is 'qout16~1', location is LC2_A11, type is buried.
-- synthesized logic cell 
_LC2_A11 = LCELL( hour00);

-- Node name is 'qout16' 
-- Equation name is 'qout16', type is output 
qout16   =  _LC2_A11;

-- Node name is 'qout17~1' 
-- Equation name is 'qout17~1', location is LC1_A17, type is buried.
-- synthesized logic cell 
_LC1_A17 = LCELL( hour01);

-- Node name is 'qout17' 
-- Equation name is 'qout17', type is output 
qout17   =  _LC1_A17;

-- Node name is 'qout18~1' 
-- Equation name is 'qout18~1', location is LC2_A24, type is buried.
-- synthesized logic cell 
_LC2_A24 = LCELL( hour02);

-- Node name is 'qout18' 
-- Equation name is 'qout18', type is output 
qout18   =  _LC2_A24;

-- Node name is 'qout19~1' 
-- Equation name is 'qout19~1', location is LC4_C14, type is buried.
-- synthesized logic cell 
_LC4_C14 = LCELL( hour03);

-- Node name is 'qout19' 
-- Equation name is 'qout19', type is output 
qout19   =  _LC4_C14;

-- Node name is 'qout20~1' 
-- Equation name is 'qout20~1', location is LC5_A21, type is buried.
-- synthesized logic cell 
_LC5_A21 = LCELL( hour10);

-- Node name is 'qout20' 
-- Equation name is 'qout20', type is output 
qout20   =  _LC5_A21;

-- Node name is 'qout21~1' 
-- Equation name is 'qout21~1', location is LC8_A13, type is buried.
-- synthesized logic cell 
_LC8_A13 = LCELL( hour11);

-- Node name is 'qout21' 
-- Equation name is 'qout21', type is output 
qout21   =  _LC8_A13;

-- Node name is 'qout22~1' 
-- Equation name is 'qout22~1', location is LC5_B5, type is buried.
-- synthesized logic cell 
_LC5_B5  = LCELL( hour12);

-- Node name is 'qout22' 
-- Equation name is 'qout22', type is output 
qout22   =  _LC5_B5;

-- Node name is 'qout23~1' 
-- Equation name is 'qout23~1', location is LC1_C5, type is buried.
-- synthesized logic cell 
_LC1_C5  = LCELL( hour13);

-- Node name is 'qout23' 
-- Equation name is 'qout23', type is output 
qout23   =  _LC1_C5;



Project Information                   d:\my_own_works\digit_clock\gather24.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,847K