📄 gather24.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\my_own_works\digit_clock\gather24.rpt
gather24
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
64 - - B -- OUTPUT 0 1 0 0 qout0
18 - - A -- OUTPUT 0 1 0 0 qout1
5 - - - 05 OUTPUT 0 1 0 0 qout2
16 - - A -- OUTPUT 0 1 0 0 qout3
11 - - - 01 OUTPUT 0 1 0 0 qout4
17 - - A -- OUTPUT 0 1 0 0 qout5
24 - - B -- OUTPUT 0 1 0 0 qout6
23 - - B -- OUTPUT 0 1 0 0 qout7
25 - - B -- OUTPUT 0 1 0 0 qout8
61 - - C -- OUTPUT 0 1 0 0 qout9
19 - - A -- OUTPUT 0 1 0 0 qout10
67 - - B -- OUTPUT 0 1 0 0 qout11
62 - - C -- OUTPUT 0 1 0 0 qout12
28 - - C -- OUTPUT 0 1 0 0 qout13
9 - - - 02 OUTPUT 0 1 0 0 qout14
37 - - - 09 OUTPUT 0 1 0 0 qout15
3 - - - 12 OUTPUT 0 1 0 0 qout16
73 - - A -- OUTPUT 0 1 0 0 qout17
72 - - A -- OUTPUT 0 1 0 0 qout18
60 - - C -- OUTPUT 0 1 0 0 qout19
70 - - A -- OUTPUT 0 1 0 0 qout20
69 - - A -- OUTPUT 0 1 0 0 qout21
35 - - - 06 OUTPUT 0 1 0 0 qout22
27 - - C -- OUTPUT 0 1 0 0 qout23
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\my_own_works\digit_clock\gather24.rpt
gather24
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 21 LCELL s 1 0 1 0 qout0~1
- 8 - A 10 LCELL s 1 0 1 0 qout1~1
- 2 - C 05 LCELL s 1 0 1 0 qout2~1
- 1 - A 11 LCELL s 1 0 1 0 qout3~1
- 1 - B 01 LCELL s 1 0 1 0 qout4~1
- 2 - A 06 LCELL s 1 0 1 0 qout5~1
- 6 - B 11 LCELL s 1 0 1 0 qout6~1
- 4 - B 09 LCELL s 1 0 1 0 qout7~1
- 8 - B 01 LCELL s 1 0 1 0 qout8~1
- 3 - C 13 LCELL s 1 0 1 0 qout9~1
- 7 - A 02 LCELL s 1 0 1 0 qout10~1
- 1 - B 15 LCELL s 1 0 1 0 qout11~1
- 1 - C 15 LCELL s 1 0 1 0 qout12~1
- 2 - C 10 LCELL s 1 0 1 0 qout13~1
- 2 - C 02 LCELL s 1 0 1 0 qout14~1
- 1 - B 09 LCELL s 1 0 1 0 qout15~1
- 2 - A 11 LCELL s 1 0 1 0 qout16~1
- 1 - A 17 LCELL s 1 0 1 0 qout17~1
- 2 - A 24 LCELL s 1 0 1 0 qout18~1
- 4 - C 14 LCELL s 1 0 1 0 qout19~1
- 5 - A 21 LCELL s 1 0 1 0 qout20~1
- 8 - A 13 LCELL s 1 0 1 0 qout21~1
- 5 - B 05 LCELL s 1 0 1 0 qout22~1
- 1 - C 05 LCELL s 1 0 1 0 qout23~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\my_own_works\digit_clock\gather24.rpt
gather24
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 4/ 48( 8%) 8/ 48( 16%) 1/16( 6%) 8/16( 50%) 0/16( 0%)
B: 6/ 96( 6%) 4/ 48( 8%) 1/ 48( 2%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 5/ 96( 5%) 2/ 48( 4%) 4/ 48( 8%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\my_own_works\digit_clock\gather24.rpt
gather24
** EQUATIONS **
hour00 : INPUT;
hour01 : INPUT;
hour02 : INPUT;
hour03 : INPUT;
hour10 : INPUT;
hour11 : INPUT;
hour12 : INPUT;
hour13 : INPUT;
min00 : INPUT;
min01 : INPUT;
min02 : INPUT;
min03 : INPUT;
min10 : INPUT;
min11 : INPUT;
min12 : INPUT;
min13 : INPUT;
sec00 : INPUT;
sec01 : INPUT;
sec02 : INPUT;
sec03 : INPUT;
sec10 : INPUT;
sec11 : INPUT;
sec12 : INPUT;
sec13 : INPUT;
-- Node name is 'qout0~1'
-- Equation name is 'qout0~1', location is LC7_B21, type is buried.
-- synthesized logic cell
_LC7_B21 = LCELL( sec00);
-- Node name is 'qout0'
-- Equation name is 'qout0', type is output
qout0 = _LC7_B21;
-- Node name is 'qout1~1'
-- Equation name is 'qout1~1', location is LC8_A10, type is buried.
-- synthesized logic cell
_LC8_A10 = LCELL( sec01);
-- Node name is 'qout1'
-- Equation name is 'qout1', type is output
qout1 = _LC8_A10;
-- Node name is 'qout2~1'
-- Equation name is 'qout2~1', location is LC2_C5, type is buried.
-- synthesized logic cell
_LC2_C5 = LCELL( sec02);
-- Node name is 'qout2'
-- Equation name is 'qout2', type is output
qout2 = _LC2_C5;
-- Node name is 'qout3~1'
-- Equation name is 'qout3~1', location is LC1_A11, type is buried.
-- synthesized logic cell
_LC1_A11 = LCELL( sec03);
-- Node name is 'qout3'
-- Equation name is 'qout3', type is output
qout3 = _LC1_A11;
-- Node name is 'qout4~1'
-- Equation name is 'qout4~1', location is LC1_B1, type is buried.
-- synthesized logic cell
_LC1_B1 = LCELL( sec10);
-- Node name is 'qout4'
-- Equation name is 'qout4', type is output
qout4 = _LC1_B1;
-- Node name is 'qout5~1'
-- Equation name is 'qout5~1', location is LC2_A6, type is buried.
-- synthesized logic cell
_LC2_A6 = LCELL( sec11);
-- Node name is 'qout5'
-- Equation name is 'qout5', type is output
qout5 = _LC2_A6;
-- Node name is 'qout6~1'
-- Equation name is 'qout6~1', location is LC6_B11, type is buried.
-- synthesized logic cell
_LC6_B11 = LCELL( sec12);
-- Node name is 'qout6'
-- Equation name is 'qout6', type is output
qout6 = _LC6_B11;
-- Node name is 'qout7~1'
-- Equation name is 'qout7~1', location is LC4_B9, type is buried.
-- synthesized logic cell
_LC4_B9 = LCELL( sec13);
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