📄 compare24.rpt
字号:
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/ 96( 9%) 0/ 48( 0%) 1/ 48( 2%) 9/16( 56%) 0/16( 0%) 0/16( 0%)
B: 13/ 96( 13%) 0/ 48( 0%) 6/ 48( 12%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
C: 10/ 96( 10%) 6/ 48( 12%) 0/ 48( 0%) 9/16( 56%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\my_own_works\digit_clock\compare24.rpt
compare24
** EQUATIONS **
in_put00 : INPUT;
in_put01 : INPUT;
in_put02 : INPUT;
in_put03 : INPUT;
in_put04 : INPUT;
in_put05 : INPUT;
in_put06 : INPUT;
in_put07 : INPUT;
in_put08 : INPUT;
in_put09 : INPUT;
in_put010 : INPUT;
in_put10 : INPUT;
in_put011 : INPUT;
in_put11 : INPUT;
in_put012 : INPUT;
in_put12 : INPUT;
in_put013 : INPUT;
in_put13 : INPUT;
in_put014 : INPUT;
in_put14 : INPUT;
in_put015 : INPUT;
in_put15 : INPUT;
in_put016 : INPUT;
in_put16 : INPUT;
in_put017 : INPUT;
in_put17 : INPUT;
in_put018 : INPUT;
in_put18 : INPUT;
in_put019 : INPUT;
in_put19 : INPUT;
in_put020 : INPUT;
in_put021 : INPUT;
in_put022 : INPUT;
in_put023 : INPUT;
in_put110 : INPUT;
in_put111 : INPUT;
in_put112 : INPUT;
in_put113 : INPUT;
in_put114 : INPUT;
in_put115 : INPUT;
in_put116 : INPUT;
in_put117 : INPUT;
in_put118 : INPUT;
in_put119 : INPUT;
in_put120 : INPUT;
in_put121 : INPUT;
in_put122 : INPUT;
in_put123 : INPUT;
-- Node name is 'ring'
-- Equation name is 'ring', type is output
ring = _LC1_B21;
-- Node name is '~149~1'
-- Equation name is '~149~1', location is LC1_A16, type is buried.
-- synthesized logic cell
_LC1_A16 = LCELL( _EQ001);
_EQ001 = in_put05 & in_put06 & in_put15 & in_put16
# in_put05 & !in_put06 & in_put15 & !in_put16
# !in_put05 & in_put06 & !in_put15 & in_put16
# !in_put05 & !in_put06 & !in_put15 & !in_put16;
-- Node name is '~149~2'
-- Equation name is '~149~2', location is LC2_A16, type is buried.
-- synthesized logic cell
_LC2_A16 = LCELL( _EQ002);
_EQ002 = in_put04 & in_put013 & in_put14 & in_put113
# !in_put04 & in_put013 & !in_put14 & in_put113
# in_put04 & !in_put013 & in_put14 & !in_put113
# !in_put04 & !in_put013 & !in_put14 & !in_put113;
-- Node name is '~149~3'
-- Equation name is '~149~3', location is LC3_A16, type is buried.
-- synthesized logic cell
_LC3_A16 = LCELL( _EQ003);
_EQ003 = in_put011 & in_put012 & in_put111 & in_put112
# in_put011 & !in_put012 & in_put111 & !in_put112
# !in_put011 & in_put012 & !in_put111 & in_put112
# !in_put011 & !in_put012 & !in_put111 & !in_put112;
-- Node name is '~149~4'
-- Equation name is '~149~4', location is LC5_A16, type is buried.
-- synthesized logic cell
_LC5_A16 = LCELL( _EQ004);
_EQ004 = in_put09 & in_put010 & in_put19 & in_put110
# in_put09 & !in_put010 & in_put19 & !in_put110
# !in_put09 & in_put010 & !in_put19 & in_put110
# !in_put09 & !in_put010 & !in_put19 & !in_put110;
-- Node name is '~149~5'
-- Equation name is '~149~5', location is LC4_A16, type is buried.
-- synthesized logic cell
_LC4_A16 = LCELL( _EQ005);
_EQ005 = _LC1_A16 & _LC2_A16 & _LC3_A16 & _LC5_A16;
-- Node name is '~149~6'
-- Equation name is '~149~6', location is LC1_C9, type is buried.
-- synthesized logic cell
_LC1_C9 = LCELL( _EQ006);
_EQ006 = in_put019 & in_put020 & in_put119 & in_put120
# in_put019 & !in_put020 & in_put119 & !in_put120
# !in_put019 & in_put020 & !in_put119 & in_put120
# !in_put019 & !in_put020 & !in_put119 & !in_put120;
-- Node name is '~149~7'
-- Equation name is '~149~7', location is LC2_C9, type is buried.
-- synthesized logic cell
_LC2_C9 = LCELL( _EQ007);
_EQ007 = in_put02 & in_put03 & in_put12 & in_put13
# in_put02 & !in_put03 & in_put12 & !in_put13
# !in_put02 & in_put03 & !in_put12 & in_put13
# !in_put02 & !in_put03 & !in_put12 & !in_put13;
-- Node name is '~149~8'
-- Equation name is '~149~8', location is LC3_C9, type is buried.
-- synthesized logic cell
_LC3_C9 = LCELL( _EQ008);
_EQ008 = in_put00 & in_put01 & in_put10 & in_put11
# in_put00 & !in_put01 & in_put10 & !in_put11
# !in_put00 & in_put01 & !in_put10 & in_put11
# !in_put00 & !in_put01 & !in_put10 & !in_put11;
-- Node name is '~149~9'
-- Equation name is '~149~9', location is LC5_C9, type is buried.
-- synthesized logic cell
_LC5_C9 = LCELL( _EQ009);
_EQ009 = in_put07 & in_put08 & in_put17 & in_put18
# in_put07 & !in_put08 & in_put17 & !in_put18
# !in_put07 & in_put08 & !in_put17 & in_put18
# !in_put07 & !in_put08 & !in_put17 & !in_put18;
-- Node name is '~149~10'
-- Equation name is '~149~10', location is LC4_C9, type is buried.
-- synthesized logic cell
_LC4_C9 = LCELL( _EQ010);
_EQ010 = _LC1_C9 & _LC2_C9 & _LC3_C9 & _LC5_C9;
-- Node name is '~149~11'
-- Equation name is '~149~11', location is LC2_B21, type is buried.
-- synthesized logic cell
_LC2_B21 = LCELL( _EQ011);
_EQ011 = in_put017 & in_put018 & in_put117 & in_put118
# in_put017 & !in_put018 & in_put117 & !in_put118
# !in_put017 & in_put018 & !in_put117 & in_put118
# !in_put017 & !in_put018 & !in_put117 & !in_put118;
-- Node name is '~149~12'
-- Equation name is '~149~12', location is LC3_B21, type is buried.
-- synthesized logic cell
_LC3_B21 = LCELL( _EQ012);
_EQ012 = in_put015 & in_put016 & in_put115 & in_put116
# in_put015 & !in_put016 & in_put115 & !in_put116
# !in_put015 & in_put016 & !in_put115 & in_put116
# !in_put015 & !in_put016 & !in_put115 & !in_put116;
-- Node name is '~149~13'
-- Equation name is '~149~13', location is LC4_B21, type is buried.
-- synthesized logic cell
_LC4_B21 = LCELL( _EQ013);
_EQ013 = in_put014 & in_put023 & in_put114 & in_put123
# !in_put014 & in_put023 & !in_put114 & in_put123
# in_put014 & !in_put023 & in_put114 & !in_put123
# !in_put014 & !in_put023 & !in_put114 & !in_put123;
-- Node name is '~149~14'
-- Equation name is '~149~14', location is LC5_B21, type is buried.
-- synthesized logic cell
_LC5_B21 = LCELL( _EQ014);
_EQ014 = _LC2_B21 & _LC3_B21 & _LC4_B21;
-- Node name is '~149~15'
-- Equation name is '~149~15', location is LC6_B21, type is buried.
-- synthesized logic cell
_LC6_B21 = LCELL( _EQ015);
_EQ015 = in_put021 & in_put022 & in_put121 & in_put122
# in_put021 & !in_put022 & in_put121 & !in_put122
# !in_put021 & in_put022 & !in_put121 & in_put122
# !in_put021 & !in_put022 & !in_put121 & !in_put122;
-- Node name is ':149'
-- Equation name is '_LC1_B21', type is buried
_LC1_B21 = LCELL( _EQ016);
_EQ016 = _LC4_A16 & _LC4_C9 & _LC5_B21 & _LC6_B21;
Project Information d:\my_own_works\digit_clock\compare24.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,398K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -