📄 compare24.rpt
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Project Information d:\my_own_works\digit_clock\compare24.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/15/2005 23:23:22
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
COMPARE24
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
compare24
EPF10K10LC84-3 48 1 0 0 0 % 16 2 %
User Pins: 48 1 0
Device-Specific Information: d:\my_own_works\digit_clock\compare24.rpt
compare24
***** Logic for device 'compare24' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
Device-Specific Information: d:\my_own_works\digit_clock\compare24.rpt
compare24
** ERROR SUMMARY **
Info: Chip 'compare24' in device 'EPF10K10LC84-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
^
i i i i i C
i i R i i i R R i n i R n n n n O
n n E n n n E E n _ n E _ _ _ _ N
_ _ S _ _ _ S V S _ p _ S G p p p p F
p p E p p p E C E p u p E N u u u u _ ^
u u R u u u R C R u t u R D t t t t # D n
t t V t t t V I V t 1 t V I 0 1 0 1 T O C
0 1 E 1 1 0 E N E 1 1 0 E N 1 1 1 1 C N E
0 8 D 0 2 7 D T D 5 3 6 D T 4 7 0 5 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | in_put04
^nCE | 14 72 | in_put012
#TDI | 15 71 | in_put19
in_put09 | 16 70 | in_put111
in_put011 | 17 69 | in_put110
in_put14 | 18 68 | GNDINT
in_put112 | 19 67 | ring
VCCINT | 20 66 | in_put123
in_put116 | 21 65 | in_put016
in_put122 | 22 EPF10K10LC84-3 64 | in_put121
in_put023 | 23 63 | VCCINT
in_put018 | 24 62 | in_put120
in_put114 | 25 61 | in_put02
GNDINT | 26 60 | in_put020
in_put17 | 27 59 | in_put03
in_put13 | 28 58 | in_put08
in_put01 | 29 57 | #TMS
in_put119 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | in_put021
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ i i R R R V G i i i V G i R i R R i i
C n n n E E E C N n n n C N n E n E E n n
C C _ _ S S S C D _ _ _ C D _ S _ S S _ _
I O p p E E E I I p p p I I p E p E E p p
N N u u R R R N N u u u N N u R u R R u u
T F t t V V V T T t t t T T t V t V V t t
I 1 0 E E E 0 0 1 1 E 0 E E 0 0
G 1 1 D D D 5 1 6 1 D 1 D D 1 2
9 3 8 7 5 2
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\my_own_works\digit_clock\compare24.rpt
compare24
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A16 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 16/22( 72%)
B21 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 18/22( 81%)
C9 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 16/22( 72%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 43/53 ( 81%)
Total logic cells used: 16/576 ( 2%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.93/4 ( 98%)
Total fan-in: 63/2304 ( 2%)
Total input pins required: 48
Total input I/O cell registers required: 0
Total output pins required: 1
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 16
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 15/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 5/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 6/0
C: 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5/0
Total: 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 5 0 0 0 0 6 0 0 0 16/0
Device-Specific Information: d:\my_own_works\digit_clock\compare24.rpt
compare24
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
11 - - - 01 INPUT 0 0 0 1 in_put00
29 - - C -- INPUT 0 0 0 1 in_put01
61 - - C -- INPUT 0 0 0 1 in_put02
59 - - C -- INPUT 0 0 0 1 in_put03
73 - - A -- INPUT 0 0 0 1 in_put04
42 - - - -- INPUT 0 0 0 1 in_put05
84 - - - -- INPUT 0 0 0 1 in_put06
6 - - - 04 INPUT 0 0 0 1 in_put07
58 - - C -- INPUT 0 0 0 1 in_put08
16 - - A -- INPUT 0 0 0 1 in_put09
79 - - - 24 INPUT 0 0 0 1 in_put010
8 - - - 03 INPUT 0 0 0 1 in_put10
17 - - A -- INPUT 0 0 0 1 in_put011
35 - - - 06 INPUT 0 0 0 1 in_put11
72 - - A -- INPUT 0 0 0 1 in_put012
7 - - - 03 INPUT 0 0 0 1 in_put12
43 - - - -- INPUT 0 0 0 1 in_put013
28 - - C -- INPUT 0 0 0 1 in_put13
81 - - - 22 INPUT 0 0 0 1 in_put014
18 - - A -- INPUT 0 0 0 1 in_put14
52 - - - 19 INPUT 0 0 0 1 in_put015
2 - - - -- INPUT 0 0 0 1 in_put15
65 - - B -- INPUT 0 0 0 1 in_put016
44 - - - -- INPUT 0 0 0 1 in_put16
49 - - - 16 INPUT 0 0 0 1 in_put017
27 - - C -- INPUT 0 0 0 1 in_put17
24 - - B -- INPUT 0 0 0 1 in_put018
10 - - - 01 INPUT 0 0 0 1 in_put18
36 - - - 07 INPUT 0 0 0 1 in_put019
71 - - A -- INPUT 0 0 0 1 in_put19
60 - - C -- INPUT 0 0 0 1 in_put020
54 - - - 21 INPUT 0 0 0 1 in_put021
53 - - - 20 INPUT 0 0 0 1 in_put022
23 - - B -- INPUT 0 0 0 1 in_put023
69 - - A -- INPUT 0 0 0 1 in_put110
70 - - A -- INPUT 0 0 0 1 in_put111
19 - - A -- INPUT 0 0 0 1 in_put112
1 - - - -- INPUT 0 0 0 1 in_put113
25 - - B -- INPUT 0 0 0 1 in_put114
78 - - - 24 INPUT 0 0 0 1 in_put115
21 - - B -- INPUT 0 0 0 1 in_put116
80 - - - 23 INPUT 0 0 0 1 in_put117
47 - - - 14 INPUT 0 0 0 1 in_put118
30 - - C -- INPUT 0 0 0 1 in_put119
62 - - C -- INPUT 0 0 0 1 in_put120
64 - - B -- INPUT 0 0 0 1 in_put121
22 - - B -- INPUT 0 0 0 1 in_put122
66 - - B -- INPUT 0 0 0 1 in_put123
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\my_own_works\digit_clock\compare24.rpt
compare24
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
67 - - B -- OUTPUT 0 1 0 0 ring
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\my_own_works\digit_clock\compare24.rpt
compare24
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 16 OR2 s 4 0 0 1 ~149~1
- 2 - A 16 OR2 s 4 0 0 1 ~149~2
- 3 - A 16 OR2 s 4 0 0 1 ~149~3
- 5 - A 16 OR2 s 4 0 0 1 ~149~4
- 4 - A 16 AND2 s 0 4 0 1 ~149~5
- 1 - C 09 OR2 s 4 0 0 1 ~149~6
- 2 - C 09 OR2 s 4 0 0 1 ~149~7
- 3 - C 09 OR2 s 4 0 0 1 ~149~8
- 5 - C 09 OR2 s 4 0 0 1 ~149~9
- 4 - C 09 AND2 s 0 4 0 1 ~149~10
- 2 - B 21 OR2 s 4 0 0 1 ~149~11
- 3 - B 21 OR2 s 4 0 0 1 ~149~12
- 4 - B 21 OR2 s 4 0 0 1 ~149~13
- 5 - B 21 AND2 s 0 3 0 1 ~149~14
- 6 - B 21 OR2 s 4 0 0 1 ~149~15
- 1 - B 21 AND2 0 4 1 0 :149
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\my_own_works\digit_clock\compare24.rpt
compare24
** FASTTRACK INTERCONNECT UTILIZATION **
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