📄 min60.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\my_own_works\digit_clock\min60.rpt
min60
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 3/ 96( 3%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\my_own_works\digit_clock\min60.rpt
min60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 fin
Device-Specific Information: d:\my_own_works\digit_clock\min60.rpt
min60
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 rst
Device-Specific Information: d:\my_own_works\digit_clock\min60.rpt
min60
** EQUATIONS **
fin : INPUT;
rst : INPUT;
-- Node name is 'full'
-- Equation name is 'full', type is output
full = _LC7_B15;
-- Node name is ':16' = 'min0_tmp0'
-- Equation name is 'min0_tmp0', location is LC3_A21, type is buried.
min0_tmp0 = DFFE( _EQ001, GLOBAL( fin), GLOBAL(!rst), VCC, VCC);
_EQ001 = _LC6_A21 & !min0_tmp0;
-- Node name is ':15' = 'min0_tmp1'
-- Equation name is 'min0_tmp1', location is LC1_A21, type is buried.
min0_tmp1 = DFFE( _EQ002, GLOBAL( fin), GLOBAL(!rst), VCC, VCC);
_EQ002 = _LC6_A21 & !min0_tmp0 & min0_tmp1
# _LC6_A21 & min0_tmp0 & !min0_tmp1;
-- Node name is ':14' = 'min0_tmp2'
-- Equation name is 'min0_tmp2', location is LC4_A21, type is buried.
min0_tmp2 = DFFE( _EQ003, GLOBAL( fin), GLOBAL(!rst), VCC, VCC);
_EQ003 = _LC6_A21 & !min0_tmp1 & min0_tmp2
# _LC6_A21 & !min0_tmp0 & min0_tmp2
# _LC6_A21 & min0_tmp0 & min0_tmp1 & !min0_tmp2;
-- Node name is ':13' = 'min0_tmp3'
-- Equation name is 'min0_tmp3', location is LC8_A21, type is buried.
min0_tmp3 = DFFE( _EQ004, GLOBAL( fin), GLOBAL(!rst), VCC, VCC);
_EQ004 = min0_tmp0 & min0_tmp1 & min0_tmp2 & !min0_tmp3
# !min0_tmp0 & !min0_tmp1 & !min0_tmp2 & min0_tmp3;
-- Node name is 'min00'
-- Equation name is 'min00', type is output
min00 = min0_tmp0;
-- Node name is ':20' = 'min1_tmp0'
-- Equation name is 'min1_tmp0', location is LC5_B15, type is buried.
min1_tmp0 = DFFE( _EQ005, GLOBAL( fin), GLOBAL(!rst), VCC, VCC);
_EQ005 = _LC6_A21 & min1_tmp0
# _LC4_B15 & !_LC6_A21 & !min1_tmp0;
-- Node name is ':19' = 'min1_tmp1'
-- Equation name is 'min1_tmp1', location is LC3_B15, type is buried.
min1_tmp1 = DFFE( _EQ006, GLOBAL( fin), GLOBAL(!rst), VCC, VCC);
_EQ006 = _LC6_A21 & min1_tmp1
# _LC4_B15 & !min1_tmp0 & min1_tmp1
# _LC4_B15 & !_LC6_A21 & min1_tmp0 & !min1_tmp1;
-- Node name is ':18' = 'min1_tmp2'
-- Equation name is 'min1_tmp2', location is LC2_B15, type is buried.
min1_tmp2 = DFFE( _EQ007, GLOBAL( fin), GLOBAL(!rst), VCC, VCC);
_EQ007 = _LC6_A21 & min1_tmp2
# _LC4_B15 & !_LC6_B15 & min1_tmp2
# _LC4_B15 & !_LC6_A21 & _LC6_B15 & !min1_tmp2;
-- Node name is ':17' = 'min1_tmp3'
-- Equation name is 'min1_tmp3', location is LC1_B15, type is buried.
min1_tmp3 = DFFE( _EQ008, GLOBAL( fin), GLOBAL(!rst), VCC, VCC);
_EQ008 = _LC6_A21 & min1_tmp3;
-- Node name is 'min01'
-- Equation name is 'min01', type is output
min01 = min0_tmp1;
-- Node name is 'min02'
-- Equation name is 'min02', type is output
min02 = min0_tmp2;
-- Node name is 'min03'
-- Equation name is 'min03', type is output
min03 = min0_tmp3;
-- Node name is 'min10'
-- Equation name is 'min10', type is output
min10 = min1_tmp0;
-- Node name is 'min11'
-- Equation name is 'min11', type is output
min11 = min1_tmp1;
-- Node name is 'min12'
-- Equation name is 'min12', type is output
min12 = min1_tmp2;
-- Node name is 'min13'
-- Equation name is 'min13', type is output
min13 = min1_tmp3;
-- Node name is '|LPM_ADD_SUB:162|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B15', type is buried
_LC6_B15 = LCELL( _EQ009);
_EQ009 = min1_tmp0 & min1_tmp1;
-- Node name is ':11'
-- Equation name is '_LC7_B15', type is buried
_LC7_B15 = DFFE( _EQ010, GLOBAL( fin), GLOBAL(!rst), VCC, VCC);
_EQ010 = !_LC4_B15 & !_LC6_A21;
-- Node name is ':83'
-- Equation name is '_LC6_A21', type is buried
!_LC6_A21 = _LC6_A21~NOT;
_LC6_A21~NOT = LCELL( _EQ011);
_EQ011 = min0_tmp0 & min0_tmp3
# min0_tmp2 & min0_tmp3
# min0_tmp1 & min0_tmp3;
-- Node name is ':112'
-- Equation name is '_LC4_B15', type is buried
_LC4_B15 = LCELL( _EQ012);
_EQ012 = !min1_tmp2 & !min1_tmp3
# !min1_tmp0 & !min1_tmp1 & !min1_tmp3;
Project Information d:\my_own_works\digit_clock\min60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,056K
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