min_out.vhd

来自「FPGA设计的时钟！很特别」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity  min_out is
	port ( set : in std_logic;       
		   alarm  : in std_logic;      
		   min60_0  ,   min60_1:     in std_logic_vector(3 downto 0);
           min_set_0,min_set_1: in std_logic_vector(3 downto 0);
           min_a_0  ,  min_a_1:  in std_logic_vector(3 downto 0);
           min0_out , min1_out: out std_logic_vector(3 downto 0));    
end  min_out;

architecture arch of min_out is
	signal min0_tmp,min1_tmp : std_logic_vector(3 downto 0);
 begin
      process ( set,alarm) 			
       begin
         if ( set='1' ) then        
			min0_tmp<=min_set_0;
			min1_tmp<=min_set_1;
		 elsif ( alarm ='1' ) then	
			min0_tmp<=min_a_0;
			min1_tmp<=min_a_1;			
             else			       
                   min0_tmp<= min60_0;
			       min1_tmp<=min60_1;
             end if;
     end process;
	min0_out<=min0_tmp;
	min1_out<=min1_tmp;

end  architecture arch;