📄 digit_clock.rpt
字号:
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\my_own_works\digit_clock\digit_clock.rpt
digit_clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 13/ 96( 13%) 4/ 48( 8%) 33/ 48( 68%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 1/ 96( 1%) 1/ 48( 2%) 3/ 48( 6%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 37/ 96( 38%) 22/ 48( 45%) 26/ 48( 54%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\my_own_works\digit_clock\digit_clock.rpt
digit_clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 hour_key
INPUT 16 min_key
INPUT 16 sec_key
DFF 9 |DIV2:14|:2
DFF 9 |SEC60:66|:11
DFF 8 |MIN60:1|:11
INPUT 2 clk
Device-Specific Information: d:\my_own_works\digit_clock\digit_clock.rpt
digit_clock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 74 rst
Device-Specific Information: d:\my_own_works\digit_clock\digit_clock.rpt
digit_clock
** EQUATIONS **
alarm : INPUT;
clk : INPUT;
hour_key : INPUT;
min_key : INPUT;
rst : INPUT;
sec_key : INPUT;
set : INPUT;
-- Node name is 'hour0_out0'
-- Equation name is 'hour0_out0', type is output
hour0_out0 = _LC2_A14;
-- Node name is 'hour0_out1'
-- Equation name is 'hour0_out1', type is output
hour0_out1 = _LC8_A14;
-- Node name is 'hour0_out2'
-- Equation name is 'hour0_out2', type is output
hour0_out2 = _LC5_A18;
-- Node name is 'hour0_out3'
-- Equation name is 'hour0_out3', type is output
hour0_out3 = _LC1_A18;
-- Node name is 'hour1_out0'
-- Equation name is 'hour1_out0', type is output
hour1_out0 = _LC2_A16;
-- Node name is 'hour1_out1'
-- Equation name is 'hour1_out1', type is output
hour1_out1 = _LC3_A18;
-- Node name is 'hour1_out2'
-- Equation name is 'hour1_out2', type is output
hour1_out2 = _LC6_A23;
-- Node name is 'hour1_out3'
-- Equation name is 'hour1_out3', type is output
hour1_out3 = _LC1_A15;
-- Node name is 'min0_out0'
-- Equation name is 'min0_out0', type is output
min0_out0 = _LC6_C6;
-- Node name is 'min0_out1'
-- Equation name is 'min0_out1', type is output
min0_out1 = _LC3_C12;
-- Node name is 'min0_out2'
-- Equation name is 'min0_out2', type is output
min0_out2 = _LC6_C4;
-- Node name is 'min0_out3'
-- Equation name is 'min0_out3', type is output
min0_out3 = _LC6_C3;
-- Node name is 'min1_out0'
-- Equation name is 'min1_out0', type is output
min1_out0 = _LC1_C7;
-- Node name is 'min1_out1'
-- Equation name is 'min1_out1', type is output
min1_out1 = _LC3_C11;
-- Node name is 'min1_out2'
-- Equation name is 'min1_out2', type is output
min1_out2 = _LC7_C20;
-- Node name is 'min1_out3'
-- Equation name is 'min1_out3', type is output
min1_out3 = _LC5_C11;
-- Node name is 'ring'
-- Equation name is 'ring', type is output
ring = _LC1_A17;
-- Node name is 'sec0_out0'
-- Equation name is 'sec0_out0', type is output
sec0_out0 = _LC6_C22;
-- Node name is 'sec0_out1'
-- Equation name is 'sec0_out1', type is output
sec0_out1 = _LC5_C21;
-- Node name is 'sec0_out2'
-- Equation name is 'sec0_out2', type is output
sec0_out2 = _LC4_C22;
-- Node name is 'sec0_out3'
-- Equation name is 'sec0_out3', type is output
sec0_out3 = _LC2_C18;
-- Node name is 'sec1_out0'
-- Equation name is 'sec1_out0', type is output
sec1_out0 = _LC5_C12;
-- Node name is 'sec1_out1'
-- Equation name is 'sec1_out1', type is output
sec1_out1 = _LC6_C12;
-- Node name is 'sec1_out2'
-- Equation name is 'sec1_out2', type is output
sec1_out2 = _LC7_C17;
-- Node name is 'sec1_out3'
-- Equation name is 'sec1_out3', type is output
sec1_out3 = _LC7_C16;
-- Node name is 'set~1'
-- Equation name is 'set~1', location is LC5_A16, type is buried.
-- synthesized logic cell
_LC5_A16 = LCELL( _EQ001);
_EQ001 = !_LC1_A20 & _LC3_A16 & !_LC7_A16 & set;
-- Node name is 'set~2'
-- Equation name is 'set~2', location is LC7_A19, type is buried.
-- synthesized logic cell
_LC7_A19 = LCELL( _EQ002);
_EQ002 = !_LC3_A24 & !_LC5_A23;
-- Node name is 'set~3'
-- Equation name is 'set~3', location is LC8_A19, type is buried.
-- synthesized logic cell
_LC8_A19 = LCELL( _EQ003);
_EQ003 = _LC2_C14 & !_LC3_A24 & _LC4_A19 & !_LC5_A23;
-- Node name is 'set~4'
-- Equation name is 'set~4', location is LC7_C23, type is buried.
-- synthesized logic cell
_LC7_C23 = LCELL( _EQ004);
_EQ004 = _LC2_C14 & _LC2_C23 & !_LC8_C19;
-- Node name is 'set~5'
-- Equation name is 'set~5', location is LC7_C10, type is buried.
-- synthesized logic cell
_LC7_C10 = LCELL( _EQ005);
_EQ005 = !_LC1_C8 & _LC2_C14 & _LC5_C10;
-- Node name is '|CHANGE:58|:33'
-- Equation name is '_LC2_C14', type is buried
!_LC2_C14 = _LC2_C14~NOT;
_LC2_C14~NOT = LCELL( _EQ006);
_EQ006 = !alarm
# set;
-- Node name is '|CHANGE:58|:72'
-- Equation name is '_LC8_C3', type is buried
_LC8_C3 = LCELL( _EQ007);
_EQ007 = alarm & _LC8_C3
# alarm & !set;
-- Node name is '|CHANGE:58|:84'
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = LCELL( _EQ008);
_EQ008 = !alarm & set
# _LC2_C15 & set;
-- Node name is '|COMPARE24:71|~149~1'
-- Equation name is '_LC3_A15', type is buried
-- synthesized logic cell
_LC3_A15 = LCELL( _EQ009);
_EQ009 = _LC1_A22 & _LC2_A19 & _LC4_A23 & _LC6_A15
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