📄 digit_clock.rpt
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- 3 - A 15 OR2 s 0 4 0 1 |COMPARE24:71|~149~1
- 6 - A 17 OR2 s 0 4 0 1 |COMPARE24:71|~149~2
- 3 - C 17 OR2 s 0 4 0 1 |COMPARE24:71|~149~3
- 3 - C 13 OR2 s 0 4 0 1 |COMPARE24:71|~149~4
- 5 - C 17 OR2 s 0 4 0 1 |COMPARE24:71|~149~5
- 1 - C 11 OR2 s 0 4 0 1 |COMPARE24:71|~149~6
- 4 - C 20 OR2 s 0 4 0 1 |COMPARE24:71|~149~7
- 6 - C 20 OR2 s 0 3 0 1 |COMPARE24:71|~149~8
- 8 - C 20 OR2 s 0 4 0 1 |COMPARE24:71|~149~9
- 6 - C 09 OR2 s 0 4 0 1 |COMPARE24:71|~149~10
- 5 - C 20 AND2 s 0 4 0 1 |COMPARE24:71|~149~11
- 2 - C 02 OR2 s 0 4 0 1 |COMPARE24:71|~149~12
- 8 - A 23 OR2 s 0 4 0 1 |COMPARE24:71|~149~13
- 1 - C 02 AND2 s 0 4 0 1 |COMPARE24:71|~149~14
- 8 - A 17 OR2 s 0 4 0 1 |COMPARE24:71|~149~15
- 1 - A 17 AND2 0 4 1 0 |COMPARE24:71|:149
- 1 - C 21 DFFE 1 1 0 9 |DIV2:14|:2
- 2 - C 21 DFFE 1 0 0 1 |DIV2:14|count (|DIV2:14|:4)
- 7 - A 20 AND2 0 3 0 1 |HOUR_SET:30|LPM_ADD_SUB:264|addcore:adder|:59
- 2 - A 20 DFFE 2 2 0 3 |HOUR_SET:30|hour0_tmp3 (|HOUR_SET:30|:21)
- 3 - A 20 DFFE 2 2 0 4 |HOUR_SET:30|hour0_tmp2 (|HOUR_SET:30|:22)
- 4 - A 20 DFFE 2 2 0 5 |HOUR_SET:30|hour0_tmp1 (|HOUR_SET:30|:23)
- 5 - A 20 DFFE 2 1 0 6 |HOUR_SET:30|hour0_tmp0 (|HOUR_SET:30|:24)
- 5 - A 15 DFFE 2 1 0 2 |HOUR_SET:30|hour1_tmp3 (|HOUR_SET:30|:25)
- 1 - A 23 DFFE 2 1 0 2 |HOUR_SET:30|hour1_tmp2 (|HOUR_SET:30|:26)
- 4 - A 16 DFFE 2 2 0 2 |HOUR_SET:30|hour1_tmp1 (|HOUR_SET:30|:27)
- 3 - A 16 DFFE 2 1 0 3 |HOUR_SET:30|hour1_tmp0 (|HOUR_SET:30|:28)
- 2 - A 24 DFFE 3 1 0 5 |HOUR_SET:30|hour0_arc3 (|HOUR_SET:30|:29)
- 4 - A 24 DFFE 3 1 0 6 |HOUR_SET:30|hour0_arc2 (|HOUR_SET:30|:30)
- 2 - A 19 DFFE 3 1 0 5 |HOUR_SET:30|hour0_arc1 (|HOUR_SET:30|:31)
- 1 - A 19 DFFE 1 2 0 5 |HOUR_SET:30|hour0_arc0 (|HOUR_SET:30|:32)
- 4 - A 23 DFFE 3 1 0 3 |HOUR_SET:30|hour1_arc3 (|HOUR_SET:30|:33)
- 2 - A 23 DFFE 3 1 0 3 |HOUR_SET:30|hour1_arc2 (|HOUR_SET:30|:34)
- 3 - A 19 DFFE 1 3 0 3 |HOUR_SET:30|hour1_arc1 (|HOUR_SET:30|:35)
- 4 - A 19 DFFE 1 3 0 3 |HOUR_SET:30|hour1_arc0 (|HOUR_SET:30|:36)
- 7 - A 16 OR2 0 3 0 4 |HOUR_SET:30|:156
- 8 - A 20 OR2 0 4 0 5 |HOUR_SET:30|:180
- 6 - A 20 AND2 ! 0 2 0 1 |HOUR_SET:30|:188
- 1 - A 20 OR2 0 4 0 3 |HOUR_SET:30|:205
- 2 - A 13 OR2 s 0 3 0 2 |HOUR_SET:30|~414~1
- 8 - A 13 AND2 s 0 2 0 3 |HOUR_SET:30|~415~1
- 1 - A 16 OR2 0 4 0 1 |HOUR_SET:30|:450
- 5 - A 23 OR2 0 3 0 4 |HOUR_SET:30|:475
- 1 - A 24 AND2 0 3 0 4 |HOUR_SET:30|:499
- 5 - A 24 OR2 0 2 0 3 |HOUR_SET:30|:507
- 3 - A 24 OR2 0 4 0 4 |HOUR_SET:30|:524
- 6 - A 19 OR2 0 3 0 1 |HOUR_SET:30|:724
- 5 - A 19 OR2 s 0 3 0 3 |HOUR_SET:30|~733~1
- 6 - A 24 AND2 s 1 2 0 2 |HOUR_SET:30|~790~1
- 8 - A 24 OR2 0 4 0 1 |HOUR_SET:30|:790
- 7 - A 24 OR2 0 3 0 1 |HOUR_SET:30|:802
- 2 - A 17 DFFE 0 4 0 4 |HOUR24:3|hour0_tmp3 (|HOUR24:3|:13)
- 3 - A 17 DFFE 0 3 0 5 |HOUR24:3|hour0_tmp2 (|HOUR24:3|:14)
- 1 - A 22 DFFE 0 3 0 4 |HOUR24:3|hour0_tmp1 (|HOUR24:3|:15)
- 2 - A 22 DFFE 0 4 0 5 |HOUR24:3|hour0_tmp0 (|HOUR24:3|:16)
- 6 - A 15 DFFE 0 2 0 3 |HOUR24:3|hour1_tmp3 (|HOUR24:3|:17)
- 4 - A 15 DFFE 0 2 0 3 |HOUR24:3|hour1_tmp2 (|HOUR24:3|:18)
- 8 - A 22 DFFE 0 4 0 3 |HOUR24:3|hour1_tmp1 (|HOUR24:3|:19)
- 3 - A 22 DFFE 0 4 0 3 |HOUR24:3|hour1_tmp0 (|HOUR24:3|:20)
- 2 - A 15 AND2 ! 0 3 0 5 |HOUR24:3|:93
- 4 - A 17 AND2 0 3 0 6 |HOUR24:3|:117
- 5 - A 17 OR2 0 2 0 3 |HOUR24:3|:125
- 5 - A 22 OR2 ! 0 4 0 3 |HOUR24:3|:142
- 7 - A 22 OR2 s 0 3 0 1 |HOUR24:3|~366~1
- 6 - A 22 AND2 s 0 2 0 4 |HOUR24:3|~367~1
- 4 - A 22 AND2 s 0 2 0 1 |HOUR24:3|~394~1
- 3 - C 06 AND2 0 2 0 1 |MIN_SET:5|LPM_ADD_SUB:307|addcore:adder|:55
- 3 - C 03 OR2 0 4 0 1 |MIN_SET:5|LPM_ADD_SUB:307|addcore:adder|:69
- 8 - C 10 AND2 0 2 0 1 |MIN_SET:5|LPM_ADD_SUB:464|addcore:adder|:55
- 7 - C 08 AND2 0 2 0 1 |MIN_SET:5|LPM_ADD_SUB:551|addcore:adder|:55
- 4 - C 03 DFFE 2 2 0 3 |MIN_SET:5|min0_tmp3 (|MIN_SET:5|:21)
- 1 - C 06 DFFE 2 2 0 3 |MIN_SET:5|min0_tmp2 (|MIN_SET:5|:22)
- 2 - C 06 DFFE 2 2 0 4 |MIN_SET:5|min0_tmp1 (|MIN_SET:5|:23)
- 5 - C 06 DFFE 2 1 0 5 |MIN_SET:5|min0_tmp0 (|MIN_SET:5|:24)
- 1 - C 05 DFFE 2 1 0 2 |MIN_SET:5|min1_tmp3 (|MIN_SET:5|:25)
- 8 - C 05 DFFE 2 2 0 3 |MIN_SET:5|min1_tmp2 (|MIN_SET:5|:26)
- 4 - C 05 DFFE 2 2 0 4 |MIN_SET:5|min1_tmp1 (|MIN_SET:5|:27)
- 5 - C 05 DFFE 2 2 0 4 |MIN_SET:5|min1_tmp0 (|MIN_SET:5|:28)
- 1 - C 03 DFFE 3 1 0 4 |MIN_SET:5|min0_arc3 (|MIN_SET:5|:29)
- 2 - C 08 DFFE 3 1 0 5 |MIN_SET:5|min0_arc2 (|MIN_SET:5|:30)
- 3 - C 08 DFFE 3 1 0 6 |MIN_SET:5|min0_arc1 (|MIN_SET:5|:31)
- 4 - C 08 DFFE 2 2 0 6 |MIN_SET:5|min0_arc0 (|MIN_SET:5|:32)
- 2 - C 10 DFFE 3 1 0 3 |MIN_SET:5|min1_arc3 (|MIN_SET:5|:33)
- 1 - C 20 DFFE 3 1 0 4 |MIN_SET:5|min1_arc2 (|MIN_SET:5|:34)
- 1 - C 10 DFFE 1 3 0 4 |MIN_SET:5|min1_arc1 (|MIN_SET:5|:35)
- 3 - C 10 DFFE 1 3 0 6 |MIN_SET:5|min1_arc0 (|MIN_SET:5|:36)
- 2 - C 03 OR2 0 4 0 9 |MIN_SET:5|:143
- 2 - C 05 OR2 0 3 0 1 |MIN_SET:5|:175
- 3 - C 05 AND2 s 0 3 0 3 |MIN_SET:5|~356~1
- 7 - C 05 OR2 0 4 0 1 |MIN_SET:5|:356
- 6 - C 05 OR2 0 3 0 1 |MIN_SET:5|:362
- 1 - C 08 OR2 0 4 0 6 |MIN_SET:5|:387
- 5 - C 10 OR2 0 4 0 4 |MIN_SET:5|:416
- 4 - C 10 OR2 0 4 0 1 |MIN_SET:5|:599
- 1 - A 08 AND2 s 1 1 0 4 |MIN_SET:5|~632~1
- 8 - C 08 OR2 0 4 0 1 |MIN_SET:5|:632
- 6 - C 08 OR2 0 4 0 1 |MIN_SET:5|:644
- 5 - C 08 OR2 0 3 0 1 |MIN_SET:5|:653
- 6 - C 10 OR2 s 0 4 0 1 |MIN_SET:5|~691~1
- 6 - C 01 AND2 0 2 0 1 |MIN60:1|LPM_ADD_SUB:162|addcore:adder|:55
- 7 - C 01 DFFE 0 3 0 8 |MIN60:1|:11
- 5 - C 09 DFFE 0 4 0 3 |MIN60:1|min0_tmp3 (|MIN60:1|:13)
- 3 - C 09 DFFE 0 4 0 4 |MIN60:1|min0_tmp2 (|MIN60:1|:14)
- 2 - C 09 DFFE 0 3 0 5 |MIN60:1|min0_tmp1 (|MIN60:1|:15)
- 4 - C 09 DFFE 0 2 0 6 |MIN60:1|min0_tmp0 (|MIN60:1|:16)
- 4 - C 01 DFFE 0 2 0 3 |MIN60:1|min1_tmp3 (|MIN60:1|:17)
- 2 - C 01 DFFE 0 4 0 3 |MIN60:1|min1_tmp2 (|MIN60:1|:18)
- 3 - C 01 DFFE 0 4 0 4 |MIN60:1|min1_tmp1 (|MIN60:1|:19)
- 1 - C 01 DFFE 0 3 0 5 |MIN60:1|min1_tmp0 (|MIN60:1|:20)
- 1 - C 09 OR2 0 4 0 8 |MIN60:1|:83
- 5 - C 01 OR2 0 4 0 4 |MIN60:1|:112
- 2 - C 22 AND2 0 2 0 1 |SEC_SET:28|LPM_ADD_SUB:307|addcore:adder|:55
- 1 - C 18 OR2 0 4 0 1 |SEC_SET:28|LPM_ADD_SUB:307|addcore:adder|:69
- 8 - C 23 AND2 0 2 0 1 |SEC_SET:28|LPM_ADD_SUB:464|addcore:adder|:55
- 7 - C 19 AND2 0 2 0 1 |SEC_SET:28|LPM_ADD_SUB:551|addcore:adder|:55
- 4 - C 18 DFFE 2 2 0 3 |SEC_SET:28|sec0_tmp3 (|SEC_SET:28|:21)
- 1 - C 22 DFFE 2 2 0 3 |SEC_SET:28|sec0_tmp2 (|SEC_SET:28|:22)
- 3 - C 18 DFFE 2 2 0 4 |SEC_SET:28|sec0_tmp1 (|SEC_SET:28|:23)
- 6 - C 18 DFFE 2 1 0 5 |SEC_SET:28|sec0_tmp0 (|SEC_SET:28|:24)
- 1 - C 24 DFFE 2 1 0 2 |SEC_SET:28|sec1_tmp3 (|SEC_SET:28|:25)
- 4 - C 24 DFFE 2 2 0 3 |SEC_SET:28|sec1_tmp2 (|SEC_SET:28|:26)
- 2 - C 24 DFFE 2 2 0 4 |SEC_SET:28|sec1_tmp1 (|SEC_SET:28|:27)
- 3 - C 24 DFFE 2 2 0 4 |SEC_SET:28|sec1_tmp0 (|SEC_SET:28|:28)
- 1 - C 15 DFFE 3 1 0 4 |SEC_SET:28|sec0_arc3 (|SEC_SET:28|:29)
- 1 - C 19 DFFE 3 1 0 5 |SEC_SET:28|sec0_arc2 (|SEC_SET:28|:30)
- 2 - C 19 DFFE 3 1 0 6 |SEC_SET:28|sec0_arc1 (|SEC_SET:28|:31)
- 3 - C 19 DFFE 3 1 0 6 |SEC_SET:28|sec0_arc0 (|SEC_SET:28|:32)
- 5 - C 23 DFFE 3 1 0 3 |SEC_SET:28|sec1_arc3 (|SEC_SET:28|:33)
- 4 - C 17 DFFE 3 1 0 4 |SEC_SET:28|sec1_arc2 (|SEC_SET:28|:34)
- 4 - C 23 DFFE 1 3 0 4 |SEC_SET:28|sec1_arc1 (|SEC_SET:28|:35)
- 6 - C 23 DFFE 1 3 0 6 |SEC_SET:28|sec1_arc0 (|SEC_SET:28|:36)
- 8 - C 18 OR2 ! 0 4 0 9 |SEC_SET:28|:143
- 5 - C 24 OR2 0 3 0 1 |SEC_SET:28|:175
- 6 - C 24 AND2 s 0 3 0 3 |SEC_SET:28|~356~1
- 8 - C 24 OR2 0 4 0 1 |SEC_SET:28|:356
- 7 - C 24 OR2 0 3 0 1 |SEC_SET:28|:362
- 8 - C 19 OR2 ! 0 4 0 6 |SEC_SET:28|:387
- 2 - C 23 OR2 0 4 0 4 |SEC_SET:28|:416
- 1 - C 23 OR2 0 4 0 1 |SEC_SET:28|:599
- 1 - C 14 AND2 s 1 1 0 4 |SEC_SET:28|~632~1
- 5 - C 19 OR2 0 4 0 1 |SEC_SET:28|:632
- 6 - C 19 OR2 0 4 0 1 |SEC_SET:28|:644
- 4 - C 19 OR2 0 3 0 1 |SEC_SET:28|:653
- 3 - C 23 OR2 s 0 4 0 1 |SEC_SET:28|~691~1
- 7 - C 13 AND2 0 2 0 1 |SEC60:66|LPM_ADD_SUB:162|addcore:adder|:55
- 4 - C 13 DFFE 0 3 0 9 |SEC60:66|:11
- 2 - C 16 DFFE 0 4 0 6 |SEC60:66|sec0_tmp3 (|SEC60:66|:13)
- 1 - C 16 DFFE 0 4 0 5 |SEC60:66|sec0_tmp2 (|SEC60:66|:14)
- 3 - C 16 DFFE 0 3 0 6 |SEC60:66|sec0_tmp1 (|SEC60:66|:15)
- 5 - C 16 DFFE 0 4 0 6 |SEC60:66|sec0_tmp0 (|SEC60:66|:16)
- 1 - C 13 DFFE 0 2 0 3 |SEC60:66|sec1_tmp3 (|SEC60:66|:17)
- 6 - C 13 DFFE 0 4 0 3 |SEC60:66|sec1_tmp2 (|SEC60:66|:18)
- 8 - C 13 DFFE 0 4 0 4 |SEC60:66|sec1_tmp1 (|SEC60:66|:19)
- 5 - C 13 DFFE 0 3 0 5 |SEC60:66|sec1_tmp0 (|SEC60:66|:20)
- 8 - C 16 OR2 0 4 0 5 |SEC60:66|:83
- 2 - C 13 OR2 0 4 0 4 |SEC60:66|:112
- 6 - C 16 OR2 0 4 0 1 |SEL0:51|:118
- 4 - C 16 OR2 0 4 0 1 |SEL0:51|:120
- 7 - C 16 OR2 0 4 1 1 |SEL0:51|:124
- 2 - C 17 OR2 0 4 0 1 |SEL0:51|:133
- 1 - C 17 OR2 0 4 0 1 |SEL0:51|:135
- 7 - C 17 OR2 0 4 1 1 |SEL0:51|:136
- 7 - C 12 OR2 0 4 0 1 |SEL0:51|:145
- 4 - C 12 OR2 0 4 0 1 |SEL0:51|:147
- 6 - C 12 OR2 0 4 1 1 |SEL0:51|:148
- 2 - C 12 OR2 0 4 0 1 |SEL0:51|:157
- 1 - C 12 OR2 0 4 0 1 |SEL0:51|:159
- 5 - C 12 OR2 0 4 1 1 |SEL0:51|:160
- 7 - C 18 OR2 0 4 0 1 |SEL0:54|:118
- 5 - C 18 OR2 0 4 0 1 |SEL0:54|:120
- 2 - C 18 OR2 0 4 1 1 |SEL0:54|:124
- 8 - C 22 OR2 0 4 0 1 |SEL0:54|:133
- 7 - C 22 OR2 0 4 0 1 |SEL0:54|:135
- 4 - C 22 OR2 0 4 1 1 |SEL0:54|:136
- 4 - C 21 OR2 0 4 0 1 |SEL0:54|:145
- 3 - C 21 OR2 0 4 0 1 |SEL0:54|:147
- 5 - C 21 OR2 0 4 1 1 |SEL0:54|:148
- 5 - C 22 OR2 0 4 0 1 |SEL0:54|:157
- 3 - C 22 OR2 0 4 0 1 |SEL0:54|:159
- 6 - C 22 OR2 0 4 1 1 |SEL0:54|:160
- 7 - C 03 OR2 0 4 0 1 |SEL0:59|:118
- 5 - C 03 OR2 0 4 0 1 |SEL0:59|:120
- 6 - C 03 OR2 0 4 1 1 |SEL0:59|:124
- 2 - C 04 OR2 0 4 0 1 |SEL0:59|:133
- 1 - C 04 OR2 0 4 0 1 |SEL0:59|:135
- 6 - C 04 OR2 0 4 1 1 |SEL0:59|:136
- 8 - C 12 OR2 0 4 0 1 |SEL0:59|:145
- 8 - C 09 OR2 0 4 0 1 |SEL0:59|:147
- 3 - C 12 OR2 0 4 1 1 |SEL0:59|:148
- 7 - C 06 OR2 0 4 0 1 |SEL0:59|:157
- 4 - C 06 OR2 0 4 0 1 |SEL0:59|:159
- 6 - C 06 OR2 0 4 1 1 |SEL0:59|:160
- 7 - C 11 OR2 0 4 0 1 |SEL0:61|:118
- 6 - C 11 OR2 0 4 0 1 |SEL0:61|:120
- 5 - C 11 OR2 0 4 1 1 |SEL0:61|:124
- 3 - C 20 OR2 0 4 0 1 |SEL0:61|:133
- 2 - C 20 OR2 0 4 0 1 |SEL0:61|:135
- 7 - C 20 OR2 0 4 1 1 |SEL0:61|:136
- 4 - C 11 OR2 0 4 0 1 |SEL0:61|:145
- 2 - C 11 OR2 0 4 0 1 |SEL0:61|:147
- 3 - C 11 OR2 0 4 1 1 |SEL0:61|:148
- 3 - C 07 OR2 0 4 0 1 |SEL0:61|:157
- 2 - C 07 OR2 0 4 0 1 |SEL0:61|:159
- 1 - C 07 OR2 0 4 1 1 |SEL0:61|:160
- 6 - A 18 OR2 0 4 0 1 |SEL0:62|:118
- 4 - A 18 OR2 0 4 0 1 |SEL0:62|:120
- 1 - A 18 OR2 0 4 1 1 |SEL0:62|:124
- 2 - A 18 OR2 0 4 0 1 |SEL0:62|:133
- 7 - A 17 OR2 0 4 0 1 |SEL0:62|:135
- 5 - A 18 OR2 0 4 1 1 |SEL0:62|:136
- 5 - A 14 OR2 0 4 0 1 |SEL0:62|:145
- 4 - A 14 OR2 0 4 0 1 |SEL0:62|:147
- 8 - A 14 OR2 0 4 1 1 |SEL0:62|:148
- 3 - A 14 OR2 0 4 0 1 |SEL0:62|:157
- 1 - A 14 OR2 0 4 0 1 |SEL0:62|:159
- 2 - A 14 OR2 0 4 1 1 |SEL0:62|:160
- 8 - A 15 OR2 0 4 0 1 |SEL0:63|:118
- 7 - A 15 OR2 0 4 0 1 |SEL0:63|:120
- 1 - A 15 OR2 0 4 1 1 |SEL0:63|:124
- 7 - A 23 OR2 0 4 0 1 |SEL0:63|:133
- 3 - A 23 OR2 0 4 0 1 |SEL0:63|:135
- 6 - A 23 OR2 0 4 1 1 |SEL0:63|:136
- 8 - A 18 OR2 0 4 0 1 |SEL0:63|:145
- 7 - A 18 OR2 0 4 0 1 |SEL0:63|:147
- 3 - A 18 OR2 0 4 1 1 |SEL0:63|:148
- 8 - A 16 OR2 0 4 0 1 |SEL0:63|:157
- 6 - A 16 OR2 0 4 0 1 |SEL0:63|:159
- 2 - A 16 OR2 0 4 1 1 |SEL0:63|:160
- 5 - A 16 AND2 s 1 3 0 1 set~1
- 7 - A 19 AND2 s 0 2 0 1 set~2
- 8 - A 19 AND2 s 0 4 0 1 set~3
- 7 - C 23 AND2 s 0 3 0 1 set~4
- 7 - C 10 AND2 s 0 3 0 1 set~5
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
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