📄 digit_clock.rpt
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JTAG User Code = 7f
h ^
m m m m o C
R h i i i i R R R R u O
E o m s n n n n E E E E r N
S u i e 0 0 0 V 0 G G G S G S S S 1 F
E r n c _ _ _ C _ N N N E N E E E _ _ ^
R _ _ _ o o o C o D D D R D R R R o # D n
V k k k u u u I u I I I V I V V V u T O C
E e e e t t t N t N N N E N E E E t C N E
D y y y 2 3 0 T 1 T T T D T D D D 2 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | hour1_out3
^nCE | 14 72 | hour1_out0
#TDI | 15 71 | hour1_out1
min1_out0 | 16 70 | hour0_out2
min1_out1 | 17 69 | RESERVED
min1_out3 | 18 68 | GNDINT
min1_out2 | 19 67 | hour0_out3
VCCINT | 20 66 | hour0_out0
RESERVED | 21 65 | hour0_out1
RESERVED | 22 EPF10K10LC84-4 64 | RESERVED
RESERVED | 23 63 | VCCINT
sec1_out1 | 24 62 | ring
sec1_out3 | 25 61 | sec0_out3
GNDINT | 26 60 | sec0_out2
RESERVED | 27 59 | sec0_out1
RESERVED | 28 58 | sec0_out0
sec1_out0 | 29 57 | #TMS
sec1_out2 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R c R a R V G r G s V G R R R R R R R
C n E l E l E C N s N e C N E E E E E E E
C C S k S a S C D t D t C D S S S S S S S
I O E E r E I I I I I E E E E E E E
N N R R m R N N N N N R R R R R R R
T F V V V T T T T T V V V V V V V
I E E E E E E E E E E
G D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\my_own_works\digit_clock\digit_clock.rpt
digit_clock
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
A13 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
A14 6/ 8( 75%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 8/22( 36%)
A15 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 11/22( 50%)
A16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 10/22( 45%)
A17 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 14/22( 63%)
A18 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
A19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
A20 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
A22 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 5/22( 22%)
A23 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 10/22( 45%)
A24 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 6/22( 27%)
C1 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 2/22( 9%)
C2 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
C3 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
C4 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
C5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
C6 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 7/22( 31%)
C7 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
C8 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 6/22( 27%)
C9 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 6/22( 27%)
C10 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 6/22( 27%)
C11 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
C12 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
C13 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
C14 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
C15 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 4/22( 18%)
C16 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 6/22( 27%)
C17 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 13/22( 59%)
C18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
C19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 5/22( 22%)
C20 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 18/22( 81%)
C21 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
C22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
C23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 6/22( 27%)
C24 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 30/53 ( 56%)
Total logic cells used: 236/576 ( 40%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.59/4 ( 89%)
Total fan-in: 848/2304 ( 36%)
Total input pins required: 7
Total input I/O cell registers required: 0
Total output pins required: 25
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 236
Total flipflops required: 76
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 33/ 576 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 1 0 0 0 0 0 2 6 8 8 8 8 8 8 0 8 8 8 81/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 7 2 8 3 8 7 3 8 7 8 7 8 0 8 2 2 8 6 8 8 8 5 8 8 8 155/0
Total: 7 2 8 3 8 7 3 9 7 8 7 8 0 10 8 10 16 14 16 16 16 5 16 16 16 236/0
Device-Specific Information: d:\my_own_works\digit_clock\digit_clock.rpt
digit_clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
38 - - - 10 INPUT 0 0 0 22 alarm
36 - - - 07 INPUT 0 0 0 2 clk
10 - - - 01 INPUT 0 0 0 16 hour_key
9 - - - 02 INPUT 0 0 0 16 min_key
42 - - - -- INPUT G 0 0 0 0 rst
8 - - - 03 INPUT 0 0 0 16 sec_key
44 - - - -- INPUT 0 0 0 45 set
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\my_own_works\digit_clock\digit_clock.rpt
digit_clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
66 - - B -- OUTPUT 0 1 0 0 hour0_out0
65 - - B -- OUTPUT 0 1 0 0 hour0_out1
70 - - A -- OUTPUT 0 1 0 0 hour0_out2
67 - - B -- OUTPUT 0 1 0 0 hour0_out3
72 - - A -- OUTPUT 0 1 0 0 hour1_out0
71 - - A -- OUTPUT 0 1 0 0 hour1_out1
78 - - - 24 OUTPUT 0 1 0 0 hour1_out2
73 - - A -- OUTPUT 0 1 0 0 hour1_out3
5 - - - 05 OUTPUT 0 1 0 0 min0_out0
3 - - - 12 OUTPUT 0 1 0 0 min0_out1
7 - - - 03 OUTPUT 0 1 0 0 min0_out2
6 - - - 04 OUTPUT 0 1 0 0 min0_out3
16 - - A -- OUTPUT 0 1 0 0 min1_out0
17 - - A -- OUTPUT 0 1 0 0 min1_out1
19 - - A -- OUTPUT 0 1 0 0 min1_out2
18 - - A -- OUTPUT 0 1 0 0 min1_out3
62 - - C -- OUTPUT 0 1 0 0 ring
58 - - C -- OUTPUT 0 1 0 0 sec0_out0
59 - - C -- OUTPUT 0 1 0 0 sec0_out1
60 - - C -- OUTPUT 0 1 0 0 sec0_out2
61 - - C -- OUTPUT 0 1 0 0 sec0_out3
29 - - C -- OUTPUT 0 1 0 0 sec1_out0
24 - - B -- OUTPUT 0 1 0 0 sec1_out1
30 - - C -- OUTPUT 0 1 0 0 sec1_out2
25 - - B -- OUTPUT 0 1 0 0 sec1_out3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\my_own_works\digit_clock\digit_clock.rpt
digit_clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 14 OR2 ! 2 0 0 11 |CHANGE:58|:33
- 8 - C 03 OR2 2 0 0 72 |CHANGE:58|:72
- 2 - C 15 OR2 2 0 0 72 |CHANGE:58|:84
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