digit_clock.rpt

FPGA设计的时钟！很特别

Project Information                d:\my_own_works\digit_clock\digit_clock.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/16/2005 00:11:33

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

digit_clock
      EPF10K10LC84-4       7      25     0    0         0  %    236      40 %

User Pins:                 7      25     0  



Project Information                d:\my_own_works\digit_clock\digit_clock.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

digit_clock@38                    alarm
digit_clock@36                    clk
digit_clock@10                    hour_key
digit_clock@66                    hour0_out0
digit_clock@65                    hour0_out1
digit_clock@70                    hour0_out2
digit_clock@67                    hour0_out3
digit_clock@72                    hour1_out0
digit_clock@71                    hour1_out1
digit_clock@78                    hour1_out2
digit_clock@73                    hour1_out3
digit_clock@9                     min_key
digit_clock@5                     min0_out0
digit_clock@3                     min0_out1
digit_clock@7                     min0_out2
digit_clock@6                     min0_out3
digit_clock@16                    min1_out0
digit_clock@17                    min1_out1
digit_clock@19                    min1_out2
digit_clock@18                    min1_out3
digit_clock@62                    ring
digit_clock@42                    rst
digit_clock@8                     sec_key
digit_clock@58                    sec0_out0
digit_clock@59                    sec0_out1
digit_clock@60                    sec0_out2
digit_clock@61                    sec0_out3
digit_clock@29                    sec1_out0
digit_clock@24                    sec1_out1
digit_clock@30                    sec1_out2
digit_clock@25                    sec1_out3
digit_clock@44                    set


Project Information                d:\my_own_works\digit_clock\digit_clock.rpt

** FILE HIERARCHY **



|min60:1|
|min60:1|lpm_add_sub:162|
|min60:1|lpm_add_sub:162|addcore:adder|
|min60:1|lpm_add_sub:162|altshift:result_ext_latency_ffs|
|min60:1|lpm_add_sub:162|altshift:carry_ext_latency_ffs|
|min60:1|lpm_add_sub:162|altshift:oflow_ext_latency_ffs|
|min60:1|lpm_add_sub:258|
|min60:1|lpm_add_sub:258|addcore:adder|
|min60:1|lpm_add_sub:258|altshift:result_ext_latency_ffs|
|min60:1|lpm_add_sub:258|altshift:carry_ext_latency_ffs|
|min60:1|lpm_add_sub:258|altshift:oflow_ext_latency_ffs|
|hour24:3|
|hour24:3|lpm_add_sub:176|
|hour24:3|lpm_add_sub:176|addcore:adder|
|hour24:3|lpm_add_sub:176|altshift:result_ext_latency_ffs|
|hour24:3|lpm_add_sub:176|altshift:carry_ext_latency_ffs|
|hour24:3|lpm_add_sub:176|altshift:oflow_ext_latency_ffs|
|hour24:3|lpm_add_sub:203|
|hour24:3|lpm_add_sub:203|addcore:adder|
|hour24:3|lpm_add_sub:203|altshift:result_ext_latency_ffs|
|hour24:3|lpm_add_sub:203|altshift:carry_ext_latency_ffs|
|hour24:3|lpm_add_sub:203|altshift:oflow_ext_latency_ffs|
|hour24:3|lpm_add_sub:313|
|hour24:3|lpm_add_sub:313|addcore:adder|
|hour24:3|lpm_add_sub:313|altshift:result_ext_latency_ffs|
|hour24:3|lpm_add_sub:313|altshift:carry_ext_latency_ffs|
|hour24:3|lpm_add_sub:313|altshift:oflow_ext_latency_ffs|
|min_set:5|
|min_set:5|lpm_add_sub:220|
|min_set:5|lpm_add_sub:220|addcore:adder|
|min_set:5|lpm_add_sub:220|altshift:result_ext_latency_ffs|
|min_set:5|lpm_add_sub:220|altshift:carry_ext_latency_ffs|
|min_set:5|lpm_add_sub:220|altshift:oflow_ext_latency_ffs|
|min_set:5|lpm_add_sub:307|
|min_set:5|lpm_add_sub:307|addcore:adder|
|min_set:5|lpm_add_sub:307|altshift:result_ext_latency_ffs|
|min_set:5|lpm_add_sub:307|altshift:carry_ext_latency_ffs|
|min_set:5|lpm_add_sub:307|altshift:oflow_ext_latency_ffs|
|min_set:5|lpm_add_sub:464|
|min_set:5|lpm_add_sub:464|addcore:adder|
|min_set:5|lpm_add_sub:464|altshift:result_ext_latency_ffs|
|min_set:5|lpm_add_sub:464|altshift:carry_ext_latency_ffs|
|min_set:5|lpm_add_sub:464|altshift:oflow_ext_latency_ffs|
|min_set:5|lpm_add_sub:551|
|min_set:5|lpm_add_sub:551|addcore:adder|
|min_set:5|lpm_add_sub:551|altshift:result_ext_latency_ffs|
|min_set:5|lpm_add_sub:551|altshift:carry_ext_latency_ffs|
|min_set:5|lpm_add_sub:551|altshift:oflow_ext_latency_ffs|
|div2:14|
|div2:14|lpm_add_sub:14|
|div2:14|lpm_add_sub:14|addcore:adder|
|div2:14|lpm_add_sub:14|altshift:result_ext_latency_ffs|
|div2:14|lpm_add_sub:14|altshift:carry_ext_latency_ffs|
|div2:14|lpm_add_sub:14|altshift:oflow_ext_latency_ffs|
|sec_set:28|
|sec_set:28|lpm_add_sub:220|
|sec_set:28|lpm_add_sub:220|addcore:adder|
|sec_set:28|lpm_add_sub:220|altshift:result_ext_latency_ffs|
|sec_set:28|lpm_add_sub:220|altshift:carry_ext_latency_ffs|
|sec_set:28|lpm_add_sub:220|altshift:oflow_ext_latency_ffs|
|sec_set:28|lpm_add_sub:307|
|sec_set:28|lpm_add_sub:307|addcore:adder|
|sec_set:28|lpm_add_sub:307|altshift:result_ext_latency_ffs|
|sec_set:28|lpm_add_sub:307|altshift:carry_ext_latency_ffs|
|sec_set:28|lpm_add_sub:307|altshift:oflow_ext_latency_ffs|
|sec_set:28|lpm_add_sub:464|
|sec_set:28|lpm_add_sub:464|addcore:adder|
|sec_set:28|lpm_add_sub:464|altshift:result_ext_latency_ffs|
|sec_set:28|lpm_add_sub:464|altshift:carry_ext_latency_ffs|
|sec_set:28|lpm_add_sub:464|altshift:oflow_ext_latency_ffs|
|sec_set:28|lpm_add_sub:551|
|sec_set:28|lpm_add_sub:551|addcore:adder|
|sec_set:28|lpm_add_sub:551|altshift:result_ext_latency_ffs|
|sec_set:28|lpm_add_sub:551|altshift:carry_ext_latency_ffs|
|sec_set:28|lpm_add_sub:551|altshift:oflow_ext_latency_ffs|
|hour_set:30|
|hour_set:30|lpm_add_sub:239|
|hour_set:30|lpm_add_sub:239|addcore:adder|
|hour_set:30|lpm_add_sub:239|altshift:result_ext_latency_ffs|
|hour_set:30|lpm_add_sub:239|altshift:carry_ext_latency_ffs|
|hour_set:30|lpm_add_sub:239|altshift:oflow_ext_latency_ffs|
|hour_set:30|lpm_add_sub:264|
|hour_set:30|lpm_add_sub:264|addcore:adder|
|hour_set:30|lpm_add_sub:264|altshift:result_ext_latency_ffs|
|hour_set:30|lpm_add_sub:264|altshift:carry_ext_latency_ffs|
|hour_set:30|lpm_add_sub:264|altshift:oflow_ext_latency_ffs|
|hour_set:30|lpm_add_sub:363|
|hour_set:30|lpm_add_sub:363|addcore:adder|
|hour_set:30|lpm_add_sub:363|altshift:result_ext_latency_ffs|
|hour_set:30|lpm_add_sub:363|altshift:carry_ext_latency_ffs|
|hour_set:30|lpm_add_sub:363|altshift:oflow_ext_latency_ffs|
|hour_set:30|lpm_add_sub:558|
|hour_set:30|lpm_add_sub:558|addcore:adder|
|hour_set:30|lpm_add_sub:558|altshift:result_ext_latency_ffs|
|hour_set:30|lpm_add_sub:558|altshift:carry_ext_latency_ffs|
|hour_set:30|lpm_add_sub:558|altshift:oflow_ext_latency_ffs|
|hour_set:30|lpm_add_sub:583|
|hour_set:30|lpm_add_sub:583|addcore:adder|
|hour_set:30|lpm_add_sub:583|altshift:result_ext_latency_ffs|
|hour_set:30|lpm_add_sub:583|altshift:carry_ext_latency_ffs|
|hour_set:30|lpm_add_sub:583|altshift:oflow_ext_latency_ffs|
|hour_set:30|lpm_add_sub:682|
|hour_set:30|lpm_add_sub:682|addcore:adder|
|hour_set:30|lpm_add_sub:682|altshift:result_ext_latency_ffs|
|hour_set:30|lpm_add_sub:682|altshift:carry_ext_latency_ffs|
|hour_set:30|lpm_add_sub:682|altshift:oflow_ext_latency_ffs|
|sel0:51|
|sel0:63|
|sel0:62|
|sel0:61|
|sel0:59|
|sel0:54|
|change:58|
|gather24:65|
|gather24:67|
|sec60:66|
|sec60:66|lpm_add_sub:162|
|sec60:66|lpm_add_sub:162|addcore:adder|
|sec60:66|lpm_add_sub:162|altshift:result_ext_latency_ffs|
|sec60:66|lpm_add_sub:162|altshift:carry_ext_latency_ffs|
|sec60:66|lpm_add_sub:162|altshift:oflow_ext_latency_ffs|
|sec60:66|lpm_add_sub:258|
|sec60:66|lpm_add_sub:258|addcore:adder|
|sec60:66|lpm_add_sub:258|altshift:result_ext_latency_ffs|
|sec60:66|lpm_add_sub:258|altshift:carry_ext_latency_ffs|
|sec60:66|lpm_add_sub:258|altshift:oflow_ext_latency_ffs|
|compare24:71|


Device-Specific Information:       d:\my_own_works\digit_clock\digit_clock.rpt
digit_clock

***** Logic for device 'digit_clock' compiled without errors.




Device: EPF10K10LC84-4

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF