sel0.vhd

FPGA设计的时钟！很特别

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY SEL0 IS
	PORT(
		data0,data1,data2: in std_logic_vector(3 downto 0);
		 sel3	         : in std_logic_vector(1 downto 0);
         sel_out         : out std_logic_vector(3 downto 0));

END SEL0;
ARCHITECTURE behav OF SEL0 IS
   
BEGIN
  PROCESS (sel3,data0,data1,data2)
    BEGIN
     if (sel3="10") then 
        sel_out<=data2;    
     elsif (sel3="01") then
            sel_out<=data1;
        elsif(sel3="00") then
           sel_out<=data0;
        else null;
  end if;
END PROCESS ;
  

END  ARCHITECTURE  behav;