📄 hour_set.rpt
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-- Equation name is 'hour1_tmp1', location is LC7_C19, type is buried.
hour1_tmp1 = DFFE( _EQ014, GLOBAL( hour_key), GLOBAL(!rst), VCC, VCC);
_EQ014 = _LC8_C19
# hour1_tmp1 & _LC6_C14
# hour1_tmp1 & !set;
-- Node name is ':26' = 'hour1_tmp2'
-- Equation name is 'hour1_tmp2', location is LC1_C16, type is buried.
hour1_tmp2 = DFFE( _EQ015, GLOBAL( hour_key), GLOBAL(!rst), VCC, VCC);
_EQ015 = hour1_tmp2 & _LC6_C14
# hour1_tmp2 & !set;
-- Node name is ':25' = 'hour1_tmp3'
-- Equation name is 'hour1_tmp3', location is LC6_C16, type is buried.
hour1_tmp3 = DFFE( _EQ016, GLOBAL( hour_key), GLOBAL(!rst), VCC, VCC);
_EQ016 = hour1_tmp3 & _LC6_C14
# hour1_tmp3 & !set;
-- Node name is 'hour01'
-- Equation name is 'hour01', type is output
hour01 = hour0_tmp1;
-- Node name is 'hour02'
-- Equation name is 'hour02', type is output
hour02 = hour0_tmp2;
-- Node name is 'hour03'
-- Equation name is 'hour03', type is output
hour03 = hour0_tmp3;
-- Node name is 'hour10'
-- Equation name is 'hour10', type is output
hour10 = hour1_tmp0;
-- Node name is 'hour11'
-- Equation name is 'hour11', type is output
hour11 = hour1_tmp1;
-- Node name is 'hour12'
-- Equation name is 'hour12', type is output
hour12 = hour1_tmp2;
-- Node name is 'hour13'
-- Equation name is 'hour13', type is output
hour13 = hour1_tmp3;
-- Node name is 'set~1'
-- Equation name is 'set~1', location is LC4_C17, type is buried.
-- synthesized logic cell
_LC4_C17 = LCELL( _EQ017);
_EQ017 = !_LC6_C19 & !_LC8_C17;
-- Node name is 'set~2'
-- Equation name is 'set~2', location is LC2_C22, type is buried.
-- synthesized logic cell
_LC2_C22 = LCELL( _EQ018);
_EQ018 = hour1_arc0 & !_LC1_C19 & !_LC6_C19 & !_LC8_C17;
-- Node name is 'set~3'
-- Equation name is 'set~3', location is LC8_C19, type is buried.
-- synthesized logic cell
_LC8_C19 = LCELL( _EQ019);
_EQ019 = hour1_tmp0 & !_LC1_C14 & !_LC8_C16 & set;
-- Node name is '|LPM_ADD_SUB:264|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C14', type is buried
_LC7_C14 = LCELL( _EQ020);
_EQ020 = hour0_tmp0 & hour0_tmp1;
-- Node name is '|LPM_ADD_SUB:264|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C14', type is buried
_LC8_C14 = LCELL( _EQ021);
_EQ021 = hour0_tmp0 & hour0_tmp1 & hour0_tmp2;
-- Node name is '|LPM_ADD_SUB:583|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C17', type is buried
!_LC3_C17 = _LC3_C17~NOT;
_LC3_C17~NOT = LCELL( _EQ022);
_EQ022 = !hour0_arc1
# !hour0_arc0;
-- Node name is ':156'
-- Equation name is '_LC8_C16', type is buried
!_LC8_C16 = _LC8_C16~NOT;
_LC8_C16~NOT = LCELL( _EQ023);
_EQ023 = !hour1_tmp1 & !hour1_tmp2 & !hour1_tmp3;
-- Node name is ':180'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = LCELL( _EQ024);
_EQ024 = !hour0_tmp1 & !hour0_tmp2 & !hour0_tmp3
# !hour0_tmp0 & !hour0_tmp2 & !hour0_tmp3;
-- Node name is ':205'
-- Equation name is '_LC1_C14', type is buried
!_LC1_C14 = _LC1_C14~NOT;
_LC1_C14~NOT = LCELL( _EQ025);
_EQ025 = hour0_tmp2 & hour0_tmp3
# hour0_tmp1 & hour0_tmp3
# hour0_tmp0 & hour0_tmp3;
-- Node name is '~414~1'
-- Equation name is '~414~1', location is LC2_C16, type is buried.
-- synthesized logic cell
_LC2_C16 = LCELL( _EQ026);
_EQ026 = _LC4_C16
# _LC6_C14 & _LC8_C16;
-- Node name is '~415~1'
-- Equation name is '~415~1', location is LC4_C16, type is buried.
-- synthesized logic cell
_LC4_C16 = LCELL( _EQ027);
_EQ027 = _LC1_C14 & !_LC8_C16;
-- Node name is ':450'
-- Equation name is '_LC2_C19', type is buried
_LC2_C19 = LCELL( _EQ028);
_EQ028 = hour1_tmp0 & _LC6_C14 & _LC8_C16
# hour1_tmp0 & _LC1_C14 & !_LC8_C16
# !hour1_tmp0 & !_LC1_C14 & !_LC8_C16;
-- Node name is ':475'
-- Equation name is '_LC6_C19', type is buried
!_LC6_C19 = _LC6_C19~NOT;
_LC6_C19~NOT = LCELL( _EQ029);
_EQ029 = !hour1_arc1 & !hour1_arc2 & !hour1_arc3;
-- Node name is ':499'
-- Equation name is '_LC3_C22', type is buried
_LC3_C22 = LCELL( _EQ030);
_EQ030 = !hour0_arc2 & !hour0_arc3 & !_LC3_C17;
-- Node name is ':524'
-- Equation name is '_LC8_C17', type is buried
!_LC8_C17 = _LC8_C17~NOT;
_LC8_C17~NOT = LCELL( _EQ031);
_EQ031 = hour0_arc2 & hour0_arc3
# hour0_arc1 & hour0_arc3
# hour0_arc0 & hour0_arc3;
-- Node name is ':724'
-- Equation name is '_LC7_C17', type is buried
_LC7_C17 = LCELL( _EQ032);
_EQ032 = !hour0_arc0 & hour0_arc1 & _LC2_C17
# hour0_arc0 & !hour0_arc1 & _LC2_C17;
-- Node name is '~733~1'
-- Equation name is '~733~1', location is LC2_C17, type is buried.
-- synthesized logic cell
_LC2_C17 = LCELL( _EQ033);
_EQ033 = !_LC6_C19 & _LC8_C17
# _LC3_C22 & _LC6_C19;
-- Node name is '~790~1'
-- Equation name is '~790~1', location is LC5_C22, type is buried.
-- synthesized logic cell
_LC5_C22 = LCELL( _EQ034);
_EQ034 = alarm & !_LC6_C19 & _LC8_C17;
-- Node name is ':790'
-- Equation name is '_LC8_C22', type is buried
_LC8_C22 = LCELL( _EQ035);
_EQ035 = !hour0_arc2 & hour0_arc3 & _LC5_C22
# hour0_arc3 & !_LC3_C17 & _LC5_C22
# hour0_arc2 & !hour0_arc3 & _LC3_C17 & _LC5_C22;
-- Node name is ':802'
-- Equation name is '_LC7_C22', type is buried
_LC7_C22 = LCELL( _EQ036);
_EQ036 = hour0_arc2 & !_LC3_C17 & _LC5_C22
# !hour0_arc2 & _LC3_C17 & _LC5_C22;
-- Node name is '~822~1'
-- Equation name is '~822~1', location is LC1_C19, type is buried.
-- synthesized logic cell
!_LC1_C19 = _LC1_C19~NOT;
_LC1_C19~NOT = LCELL( _EQ037);
_EQ037 = alarm & !set;
Project Information d:\my_own_works\digit_clock\hour_set.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,821K
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