📄 min_set.rpt
字号:
-- Node name is ':27' = 'min1_tmp1'
-- Equation name is 'min1_tmp1', location is LC1_C14, type is buried.
min1_tmp1 = DFFE( _EQ014, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ014 = _LC8_C9 & min1_tmp1
# _LC7_C14 & set
# min1_tmp1 & !set;
-- Node name is ':26' = 'min1_tmp2'
-- Equation name is 'min1_tmp2', location is LC6_C14, type is buried.
min1_tmp2 = DFFE( _EQ015, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ015 = _LC8_C9 & min1_tmp2
# _LC8_C14 & set
# min1_tmp2 & !set;
-- Node name is ':25' = 'min1_tmp3'
-- Equation name is 'min1_tmp3', location is LC3_C14, type is buried.
min1_tmp3 = DFFE( _EQ016, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ016 = _LC8_C9 & min1_tmp3
# min1_tmp3 & !set;
-- Node name is 'min01'
-- Equation name is 'min01', type is output
min01 = min0_tmp1;
-- Node name is 'min02'
-- Equation name is 'min02', type is output
min02 = min0_tmp2;
-- Node name is 'min03'
-- Equation name is 'min03', type is output
min03 = min0_tmp3;
-- Node name is 'min10'
-- Equation name is 'min10', type is output
min10 = min1_tmp0;
-- Node name is 'min11'
-- Equation name is 'min11', type is output
min11 = min1_tmp1;
-- Node name is 'min12'
-- Equation name is 'min12', type is output
min12 = min1_tmp2;
-- Node name is 'min13'
-- Equation name is 'min13', type is output
min13 = min1_tmp3;
-- Node name is 'set~1'
-- Equation name is 'set~1', location is LC6_B21, type is buried.
-- synthesized logic cell
_LC6_B21 = LCELL( _EQ017);
_EQ017 = _LC1_B21 & !_LC2_B21 & !_LC7_B15;
-- Node name is '|LPM_ADD_SUB:307|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C9', type is buried
_LC2_C9 = LCELL( _EQ018);
_EQ018 = min0_tmp0 & min0_tmp1;
-- Node name is '|LPM_ADD_SUB:307|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_C9', type is buried
_LC4_C9 = LCELL( _EQ019);
_EQ019 = !min0_tmp1 & min0_tmp3
# !min0_tmp0 & min0_tmp3
# !min0_tmp2 & min0_tmp3
# min0_tmp0 & min0_tmp1 & min0_tmp2 & !min0_tmp3;
-- Node name is '|LPM_ADD_SUB:464|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ020);
_EQ020 = min1_arc0 & min1_arc1;
-- Node name is '|LPM_ADD_SUB:551|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B15', type is buried
_LC8_B15 = LCELL( _EQ021);
_EQ021 = min0_arc0 & min0_arc1;
-- Node name is ':143'
-- Equation name is '_LC8_C9', type is buried
!_LC8_C9 = _LC8_C9~NOT;
_LC8_C9~NOT = LCELL( _EQ022);
_EQ022 = min0_tmp0 & min0_tmp3
# min0_tmp2 & min0_tmp3
# min0_tmp1 & min0_tmp3;
-- Node name is ':175'
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = LCELL( _EQ023);
_EQ023 = !min1_tmp2
# !min1_tmp0 & !min1_tmp1;
-- Node name is '~356~1'
-- Equation name is '~356~1', location is LC5_C14, type is buried.
-- synthesized logic cell
_LC5_C14 = LCELL( _EQ024);
_EQ024 = _LC2_C14 & !_LC8_C9 & !min1_tmp3;
-- Node name is ':356'
-- Equation name is '_LC8_C14', type is buried
_LC8_C14 = LCELL( _EQ025);
_EQ025 = _LC5_C14 & !min1_tmp1 & min1_tmp2
# _LC5_C14 & !min1_tmp0 & min1_tmp2
# _LC5_C14 & min1_tmp0 & min1_tmp1 & !min1_tmp2;
-- Node name is ':362'
-- Equation name is '_LC7_C14', type is buried
_LC7_C14 = LCELL( _EQ026);
_EQ026 = _LC5_C14 & !min1_tmp0 & min1_tmp1
# _LC5_C14 & min1_tmp0 & !min1_tmp1;
-- Node name is ':387'
-- Equation name is '_LC7_B15', type is buried
!_LC7_B15 = _LC7_B15~NOT;
_LC7_B15~NOT = LCELL( _EQ027);
_EQ027 = min0_arc2 & min0_arc3
# min0_arc1 & min0_arc3
# min0_arc0 & min0_arc3;
-- Node name is ':416'
-- Equation name is '_LC1_B21', type is buried
_LC1_B21 = LCELL( _EQ028);
_EQ028 = !min1_arc2 & !min1_arc3
# !min1_arc0 & !min1_arc1 & !min1_arc3;
-- Node name is ':599'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = LCELL( _EQ029);
_EQ029 = _LC7_B15 & min1_arc2
# _LC1_B21 & !_LC3_B21 & min1_arc2
# _LC1_B21 & _LC3_B21 & !_LC7_B15 & !min1_arc2;
-- Node name is '~632~1'
-- Equation name is '~632~1', location is LC5_B20, type is buried.
-- synthesized logic cell
_LC5_B20 = LCELL( _EQ030);
_EQ030 = alarm & _LC7_B15;
-- Node name is ':632'
-- Equation name is '_LC6_B15', type is buried
_LC6_B15 = LCELL( _EQ031);
_EQ031 = _LC5_B20 & !_LC8_B15 & min0_arc3
# _LC5_B20 & !min0_arc2 & min0_arc3
# _LC5_B20 & _LC8_B15 & min0_arc2 & !min0_arc3;
-- Node name is ':644'
-- Equation name is '_LC4_B15', type is buried
_LC4_B15 = LCELL( _EQ032);
_EQ032 = _LC5_B20 & !min0_arc1 & min0_arc2
# _LC5_B20 & !min0_arc0 & min0_arc2
# _LC5_B20 & min0_arc0 & min0_arc1 & !min0_arc2;
-- Node name is ':653'
-- Equation name is '_LC2_B15', type is buried
_LC2_B15 = LCELL( _EQ033);
_EQ033 = _LC5_B20 & !min0_arc0 & min0_arc1
# _LC5_B20 & min0_arc0 & !min0_arc1;
-- Node name is '~664~1'
-- Equation name is '~664~1', location is LC2_B21, type is buried.
-- synthesized logic cell
!_LC2_B21 = _LC2_B21~NOT;
_LC2_B21~NOT = LCELL( _EQ034);
_EQ034 = alarm & !set;
-- Node name is '~691~1'
-- Equation name is '~691~1', location is LC5_B21, type is buried.
-- synthesized logic cell
_LC5_B21 = LCELL( _EQ035);
_EQ035 = _LC1_B21 & !min1_arc0
# _LC2_B21
# _LC7_B15;
Project Information d:\my_own_works\digit_clock\min_set.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,592K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -