📄 min_set.rpt
字号:
61 - - C -- OUTPUT 0 1 0 0 min13
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\my_own_works\digit_clock\min_set.rpt
min_set
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 09 AND2 0 2 0 1 |LPM_ADD_SUB:307|addcore:adder|:55
- 4 - C 09 OR2 0 4 0 1 |LPM_ADD_SUB:307|addcore:adder|:69
- 3 - B 21 AND2 0 2 0 1 |LPM_ADD_SUB:464|addcore:adder|:55
- 8 - B 15 AND2 0 2 0 1 |LPM_ADD_SUB:551|addcore:adder|:55
- 6 - B 21 AND2 s 0 3 0 1 set~1
- 3 - C 09 DFFE + 1 2 1 2 min0_tmp3 (:21)
- 1 - C 09 DFFE + 1 2 1 2 min0_tmp2 (:22)
- 7 - C 09 DFFE + 1 2 1 3 min0_tmp1 (:23)
- 5 - C 09 DFFE + 1 1 1 4 min0_tmp0 (:24)
- 3 - C 14 DFFE + 1 1 1 1 min1_tmp3 (:25)
- 6 - C 14 DFFE + 1 2 1 2 min1_tmp2 (:26)
- 1 - C 14 DFFE + 1 2 1 3 min1_tmp1 (:27)
- 4 - C 14 DFFE + 1 2 1 3 min1_tmp0 (:28)
- 1 - B 20 DFFE + 2 1 1 2 min0_arc3 (:29)
- 1 - B 15 DFFE + 2 1 1 3 min0_arc2 (:30)
- 3 - B 15 DFFE + 2 1 1 4 min0_arc1 (:31)
- 5 - B 15 DFFE + 2 1 1 4 min0_arc0 (:32)
- 7 - B 21 DFFE + 2 1 1 1 min1_arc3 (:33)
- 6 - B 20 DFFE + 2 1 1 2 min1_arc2 (:34)
- 4 - B 21 DFFE + 0 3 1 2 min1_arc1 (:35)
- 8 - B 21 DFFE + 0 3 1 4 min1_arc0 (:36)
- 8 - C 09 OR2 ! 0 4 0 9 :143
- 2 - C 14 OR2 0 3 0 1 :175
- 5 - C 14 AND2 s 0 3 0 3 ~356~1
- 8 - C 14 OR2 0 4 0 1 :356
- 7 - C 14 OR2 0 3 0 1 :362
- 7 - B 15 OR2 ! 0 4 0 6 :387
- 1 - B 21 OR2 0 4 0 4 :416
- 2 - B 20 OR2 0 4 0 1 :599
- 5 - B 20 AND2 s 1 1 0 4 ~632~1
- 6 - B 15 OR2 0 4 0 1 :632
- 4 - B 15 OR2 0 4 0 1 :644
- 2 - B 15 OR2 0 3 0 1 :653
- 2 - B 21 AND2 s ! 2 0 0 3 ~664~1
- 5 - B 21 OR2 s 0 4 0 1 ~691~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\my_own_works\digit_clock\min_set.rpt
min_set
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 1/ 96( 1%) 4/ 48( 8%) 4/ 48( 8%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\my_own_works\digit_clock\min_set.rpt
min_set
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 min_key
Device-Specific Information: d:\my_own_works\digit_clock\min_set.rpt
min_set
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 16 rst
Device-Specific Information: d:\my_own_works\digit_clock\min_set.rpt
min_set
** EQUATIONS **
alarm : INPUT;
min_key : INPUT;
rst : INPUT;
set : INPUT;
-- Node name is ':32' = 'min0_arc0'
-- Equation name is 'min0_arc0', location is LC5_B15, type is buried.
min0_arc0 = DFFE( _EQ001, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ001 = _LC5_B20 & !min0_arc0 & !set
# min0_arc0 & set
# !alarm & min0_arc0;
-- Node name is ':31' = 'min0_arc1'
-- Equation name is 'min0_arc1', location is LC3_B15, type is buried.
min0_arc1 = DFFE( _EQ002, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ002 = _LC2_B15 & !set
# !alarm & min0_arc1
# min0_arc1 & set;
-- Node name is ':30' = 'min0_arc2'
-- Equation name is 'min0_arc2', location is LC1_B15, type is buried.
min0_arc2 = DFFE( _EQ003, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ003 = _LC4_B15 & !set
# !alarm & min0_arc2
# min0_arc2 & set;
-- Node name is ':29' = 'min0_arc3'
-- Equation name is 'min0_arc3', location is LC1_B20, type is buried.
min0_arc3 = DFFE( _EQ004, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ004 = _LC6_B15 & !set
# !alarm & min0_arc3
# min0_arc3 & set;
-- Node name is 'min0_a0'
-- Equation name is 'min0_a0', type is output
min0_a0 = min0_arc0;
-- Node name is 'min0_a1'
-- Equation name is 'min0_a1', type is output
min0_a1 = min0_arc1;
-- Node name is 'min0_a2'
-- Equation name is 'min0_a2', type is output
min0_a2 = min0_arc2;
-- Node name is 'min0_a3'
-- Equation name is 'min0_a3', type is output
min0_a3 = min0_arc3;
-- Node name is ':24' = 'min0_tmp0'
-- Equation name is 'min0_tmp0', location is LC5_C9, type is buried.
min0_tmp0 = DFFE( _EQ005, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ005 = _LC8_C9 & !min0_tmp0 & set
# min0_tmp0 & !set;
-- Node name is ':23' = 'min0_tmp1'
-- Equation name is 'min0_tmp1', location is LC7_C9, type is buried.
min0_tmp1 = DFFE( _EQ006, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ006 = _LC8_C9 & !min0_tmp0 & min0_tmp1
# _LC8_C9 & min0_tmp0 & !min0_tmp1 & set
# min0_tmp1 & !set;
-- Node name is ':22' = 'min0_tmp2'
-- Equation name is 'min0_tmp2', location is LC1_C9, type is buried.
min0_tmp2 = DFFE( _EQ007, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ007 = !_LC2_C9 & _LC8_C9 & min0_tmp2
# _LC2_C9 & _LC8_C9 & !min0_tmp2 & set
# min0_tmp2 & !set;
-- Node name is ':21' = 'min0_tmp3'
-- Equation name is 'min0_tmp3', location is LC3_C9, type is buried.
min0_tmp3 = DFFE( _EQ008, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ008 = _LC4_C9 & _LC8_C9 & set
# min0_tmp3 & !set;
-- Node name is 'min00'
-- Equation name is 'min00', type is output
min00 = min0_tmp0;
-- Node name is ':36' = 'min1_arc0'
-- Equation name is 'min1_arc0', location is LC8_B21, type is buried.
min1_arc0 = DFFE( _EQ009, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ009 = _LC2_B21 & min1_arc0
# _LC7_B15 & min1_arc0
# _LC1_B21 & !_LC2_B21 & !_LC7_B15 & !min1_arc0;
-- Node name is ':35' = 'min1_arc1'
-- Equation name is 'min1_arc1', location is LC4_B21, type is buried.
min1_arc1 = DFFE( _EQ010, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ010 = _LC5_B21 & min1_arc1
# _LC6_B21 & min1_arc0 & !min1_arc1;
-- Node name is ':34' = 'min1_arc2'
-- Equation name is 'min1_arc2', location is LC6_B20, type is buried.
min1_arc2 = DFFE( _EQ011, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ011 = alarm & _LC2_B20 & !set
# !alarm & min1_arc2
# min1_arc2 & set;
-- Node name is ':33' = 'min1_arc3'
-- Equation name is 'min1_arc3', location is LC7_B21, type is buried.
min1_arc3 = DFFE( _EQ012, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ012 = min1_arc3 & set
# !alarm & min1_arc3
# _LC7_B15 & min1_arc3;
-- Node name is 'min1_a0'
-- Equation name is 'min1_a0', type is output
min1_a0 = min1_arc0;
-- Node name is 'min1_a1'
-- Equation name is 'min1_a1', type is output
min1_a1 = min1_arc1;
-- Node name is 'min1_a2'
-- Equation name is 'min1_a2', type is output
min1_a2 = min1_arc2;
-- Node name is 'min1_a3'
-- Equation name is 'min1_a3', type is output
min1_a3 = min1_arc3;
-- Node name is ':28' = 'min1_tmp0'
-- Equation name is 'min1_tmp0', location is LC4_C14, type is buried.
min1_tmp0 = DFFE( _EQ013, GLOBAL( min_key), GLOBAL(!rst), VCC, VCC);
_EQ013 = _LC8_C9 & min1_tmp0
# min1_tmp0 & !set
# _LC5_C14 & !min1_tmp0 & set;
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