lib.dls

FPGA设计的时钟！很特别

DLSL
1
CHANGE.VHDLVIEW U2495764.DLS
CHANGE-ARCH.SYNTHESISVIEW U0505525.DLS
CHANGE-ARCH.VHDLVIEW U0357303.DLS
COMPARE24.VHDLVIEW U7050193.DLS
COMPARE24-ARCH.SYNTHESISVIEW U5824449.DLS
COMPARE24-ARCH.VHDLVIEW U6661527.DLS
DIV1024.VHDLVIEW U6328079.DLS
DIV1024-ARCH.SYNTHESISVIEW U9350107.DLS
DIV1024-ARCH.VHDLVIEW U7898089.DLS
DIV2.VHDLVIEW U6820758.DLS
DIV2-ARCH.SYNTHESISVIEW U4620997.DLS
DIV2-ARCH.VHDLVIEW U4181031.DLS
GATHER24.VHDLVIEW U3466564.DLS
GATHER24-ARCH.SYNTHESISVIEW U0242552.DLS
GATHER24-ARCH.VHDLVIEW U2044176.DLS
HOUR24.VHDLVIEW U8695854.DLS
HOUR24-ARCH.SYNTHESISVIEW U5172652.DLS
HOUR24-ARCH.VHDLVIEW U0805053.DLS
HOUR_OUT.VHDLVIEW U7325906.DLS
HOUR_OUT-ARCH.SYNTHESISVIEW U2611143.DLS
HOUR_OUT-ARCH.VHDLVIEW U5671632.DLS
HOUR_SET.VHDLVIEW U6280144.DLS
HOUR_SET-ARCH.SYNTHESISVIEW U3426873.DLS
HOUR_SET-ARCH.VHDLVIEW U7662857.DLS
LED.VHDLVIEW U6477842.DLS
LED-BEHV.SYNTHESISVIEW U8311426.DLS
LED-BEHV.VHDLVIEW U9822386.DLS
MIN60.VHDLVIEW U4405230.DLS
MIN60-ARCH.SYNTHESISVIEW U4580543.DLS
MIN60-ARCH.VHDLVIEW U2464893.DLS
MIN_OUT.VHDLVIEW U9768274.DLS
MIN_OUT-ARCH.SYNTHESISVIEW U1373730.DLS
MIN_OUT-ARCH.VHDLVIEW U4374728.DLS
MIN_SET.VHDLVIEW U5299043.DLS
MIN_SET-ARCH.SYNTHESISVIEW U2084438.DLS
MIN_SET-ARCH.VHDLVIEW U8108797.DLS
SEC60.VHDLVIEW U8461873.DLS
SEC60-ARCH.SYNTHESISVIEW U3570221.DLS
SEC60-ARCH.VHDLVIEW U8447045.DLS
SEC_OUT.VHDLVIEW U7998612.DLS
SEC_OUT-ARCH.SYNTHESISVIEW U3799887.DLS
SEC_OUT-ARCH.VHDLVIEW U0952761.DLS
SEC_SET.VHDLVIEW U8733808.DLS
SEC_SET-ARCH.SYNTHESISVIEW U5019379.DLS
SEC_SET-ARCH.VHDLVIEW U9919664.DLS
SEL.VHDLVIEW U5688779.DLS
SEL-BEHV.SYNTHESISVIEW U7284097.DLS
SEL-BEHV.VHDLVIEW U2219805.DLS
SEL0.VHDLVIEW U4168405.DLS
SEL0-BEHAV.SYNTHESISVIEW U8487879.DLS
SEL0-BEHAV.VHDLVIEW U4045943.DLS