📄 sel0.rpt
字号:
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\my_own_works\digit_clock\sel0.rpt
sel0
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 2/ 48( 4%) 0/ 48( 0%) 5/16( 31%) 2/16( 12%) 0/16( 0%)
C: 3/ 96( 3%) 2/ 48( 4%) 0/ 48( 0%) 3/16( 18%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\my_own_works\digit_clock\sel0.rpt
sel0
** EQUATIONS **
data00 : INPUT;
data01 : INPUT;
data02 : INPUT;
data03 : INPUT;
data10 : INPUT;
data11 : INPUT;
data12 : INPUT;
data13 : INPUT;
data20 : INPUT;
data21 : INPUT;
data22 : INPUT;
data23 : INPUT;
sel30 : INPUT;
sel31 : INPUT;
-- Node name is 'sel_out0'
-- Equation name is 'sel_out0', type is output
sel_out0 = _LC8_B2;
-- Node name is 'sel_out1'
-- Equation name is 'sel_out1', type is output
sel_out1 = _LC6_B2;
-- Node name is 'sel_out2'
-- Equation name is 'sel_out2', type is output
sel_out2 = _LC2_B2;
-- Node name is 'sel_out3'
-- Equation name is 'sel_out3', type is output
sel_out3 = _LC5_C7;
-- Node name is ':118'
-- Equation name is '_LC3_C7', type is buried
_LC3_C7 = LCELL( _EQ001);
_EQ001 = _LC2_C7
# data13 & sel30 & !sel31;
-- Node name is ':120'
-- Equation name is '_LC2_C7', type is buried
_LC2_C7 = LCELL( _EQ002);
_EQ002 = _LC5_C7 & sel31
# data03 & !sel30 & !sel31;
-- Node name is ':124'
-- Equation name is '_LC5_C7', type is buried
_LC5_C7 = LCELL( _EQ003);
_EQ003 = _LC3_C7 & !sel31
# _LC3_C7 & sel30
# data23 & !sel30 & sel31;
-- Node name is ':133'
-- Equation name is '_LC7_B2', type is buried
_LC7_B2 = LCELL( _EQ004);
_EQ004 = _LC5_B2
# data12 & sel30 & !sel31;
-- Node name is ':135'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = LCELL( _EQ005);
_EQ005 = _LC2_B2 & sel31
# data02 & !sel30 & !sel31;
-- Node name is ':136'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = LCELL( _EQ006);
_EQ006 = _LC7_B2 & !sel31
# _LC7_B2 & sel30
# data22 & !sel30 & sel31;
-- Node name is ':145'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = LCELL( _EQ007);
_EQ007 = _LC1_C7
# data11 & sel30 & !sel31;
-- Node name is ':147'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = LCELL( _EQ008);
_EQ008 = _LC6_B2 & sel31
# data01 & !sel30 & !sel31;
-- Node name is ':148'
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = LCELL( _EQ009);
_EQ009 = _LC4_B2 & !sel31
# _LC4_B2 & sel30
# data21 & !sel30 & sel31;
-- Node name is ':157'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = LCELL( _EQ010);
_EQ010 = _LC1_B2
# data10 & sel30 & !sel31;
-- Node name is ':159'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ011);
_EQ011 = _LC8_B2 & sel31
# data00 & !sel30 & !sel31;
-- Node name is ':160'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = LCELL( _EQ012);
_EQ012 = _LC3_B2 & !sel31
# _LC3_B2 & sel30
# data20 & !sel30 & sel31;
Project Information d:\my_own_works\digit_clock\sel0.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,742K
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