compare24.vhd

来自「FPGA设计的时钟！很特别」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compare24 is
	port ( in_put0,in_put1 : in std_logic_vector(23 downto 0);       
		        
		   ring     : out std_logic);
end compare24;

architecture arch of compare24 is
	begin
        process ( in_put0,in_put1)
	begin

			if ( in_put0=in_put1 ) then       
			    ring<='1';
			else
				ring<='0';
			end if;
      end process;
	 end arch;